/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.16 2003/04/06 20:36:36 martin Exp $ *//* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, *                      Precision Insight, Inc., Cedar Park, Texas, and *                      VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. *//* * Authors: *   Rickard E. Faith <faith@valinux.com> *   Kevin E. Martin <martin@valinux.com> *   Gareth Hughes <gareth@valinux.com> * * References: * *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April *   1999. * *   RAGE 128 Software Development Manual (Technical Reference Manual P/N *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * */#ifndef _R128_REG_H_#define _R128_REG_H_#include "compiler.h"				/* Memory mapped register access macros */#define INREG8(addr)        MMIO_IN8(R128MMIO, addr)#define INREG16(addr)       MMIO_IN16(R128MMIO, addr)#define INREG(addr)         MMIO_IN32(R128MMIO, addr)#define OUTREG8(addr, val)  MMIO_OUT8(R128MMIO, addr, val)#define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val)#define OUTREG(addr, val)   MMIO_OUT32(R128MMIO, addr, val)#define ADDRREG(addr)       ((volatile CARD32 *)(pointer)(R128MMIO + (addr)))#define OUTREGP(addr, val, mask)   \    do {                           \	CARD32 tmp = INREG(addr);  \	tmp &= (mask);             \	tmp |= ((val) & ~(mask));  \	OUTREG(addr, tmp);         \    } while (0)#define INPLL(pScrn, addr) R128INPLL(pScrn, addr)#define OUTPLL(addr, val)                                                 \    do {                                                                  \	OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \	OUTREG(R128_CLOCK_CNTL_DATA, val);                                \    } while (0)#define OUTPLLP(pScrn, addr, val, mask)                                   \    do {                                                                  \	CARD32 tmp = INPLL(pScrn, addr);                                  \	tmp &= (mask);                                                    \	tmp |= ((val) & ~(mask));                                         \	OUTPLL(addr, tmp);                                                \    } while (0)#define OUTPAL_START(idx)                                                 \    do {                                                                  \	OUTREG8(R128_PALETTE_INDEX, (idx));                               \    } while (0)#define OUTPAL_NEXT(r, g, b)                                              \    do {                                                                  \	OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));        \    } while (0)#define OUTPAL_NEXT_CARD32(v)                                             \    do {                                                                  \	OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff));                      \    } while (0)#define OUTPAL(idx, r, g, b)                                              \    do {                                                                  \	OUTPAL_START((idx));                                              \	OUTPAL_NEXT((r), (g), (b));                                       \    } while (0)#define INPAL_START(idx)                                                  \    do {                                                                  \	OUTREG(R128_PALETTE_INDEX, (idx) << 16);                          \    } while (0)#define INPAL_NEXT() INREG(R128_PALETTE_DATA)#define PAL_SELECT(idx)                                                   \    do {                                                                  \	CARD32 tmp = INREG(R128_DAC_CNTL);                                \	if (idx) {                                                        \	    OUTREG(R128_DAC_CNTL, tmp | R128_DAC_PALETTE_ACC_CTL);        \	} else {                                                          \	    OUTREG(R128_DAC_CNTL, tmp &                                   \		   (CARD32)~R128_DAC_PALETTE_ACC_CTL);                    \	}                                                                 \    } while (0)#define R128_ADAPTER_ID                   0x0f2c /* PCI */#define R128_AGP_APER_OFFSET              0x0178#define R128_AGP_BASE                     0x0170#define R128_AGP_CNTL                     0x0174#       define R128_AGP_APER_SIZE_256MB   (0x00 << 0)#       define R128_AGP_APER_SIZE_128MB   (0x20 << 0)#       define R128_AGP_APER_SIZE_64MB    (0x30 << 0)#       define R128_AGP_APER_SIZE_32MB    (0x38 << 0)#       define R128_AGP_APER_SIZE_16MB    (0x3c << 0)#       define R128_AGP_APER_SIZE_8MB     (0x3e << 0)#       define R128_AGP_APER_SIZE_4MB     (0x3f << 0)#       define R128_AGP_APER_SIZE_MASK    (0x3f << 0)#define R128_AGP_CNTL_B                   0x0b44#define R128_AGP_COMMAND                  0x0f58 /* PCI */#define R128_AGP_PLL_CNTL                 0x0010 /* PLL */#define R128_AGP_STATUS                   0x0f54 /* PCI */#       define R128_AGP_1X_MODE           0x01#       define R128_AGP_2X_MODE           0x02#       define R128_AGP_4X_MODE           0x04#       define R128_AGP_MODE_MASK         0x07#define R128_AMCGPIO_A_REG                0x01a0#define R128_AMCGPIO_EN_REG               0x01a8#define R128_AMCGPIO_MASK                 0x0194#define R128_AMCGPIO_Y_REG                0x01a4#define R128_ATTRDR                       0x03c1 /* VGA */#define R128_ATTRDW                       0x03c0 /* VGA */#define R128_ATTRX                        0x03c0 /* VGA */#define R128_AUX_SC_CNTL                  0x1660#       define R128_AUX1_SC_EN            (1 << 0)#       define R128_AUX1_SC_MODE_OR       (0 << 1)#       define R128_AUX1_SC_MODE_NAND     (1 << 1)#       define R128_AUX2_SC_EN            (1 << 2)#       define R128_AUX2_SC_MODE_OR       (0 << 3)#       define R128_AUX2_SC_MODE_NAND     (1 << 3)#       define R128_AUX3_SC_EN            (1 << 4)#       define R128_AUX3_SC_MODE_OR       (0 << 5)#       define R128_AUX3_SC_MODE_NAND     (1 << 5)#define R128_AUX1_SC_BOTTOM               0x1670#define R128_AUX1_SC_LEFT                 0x1664#define R128_AUX1_SC_RIGHT                0x1668#define R128_AUX1_SC_TOP                  0x166c#define R128_AUX2_SC_BOTTOM               0x1680#define R128_AUX2_SC_LEFT                 0x1674#define R128_AUX2_SC_RIGHT                0x1678#define R128_AUX2_SC_TOP                  0x167c#define R128_AUX3_SC_BOTTOM               0x1690#define R128_AUX3_SC_LEFT                 0x1684#define R128_AUX3_SC_RIGHT                0x1688#define R128_AUX3_SC_TOP                  0x168c#define R128_AUX_WINDOW_HORZ_CNTL         0x02d8#define R128_AUX_WINDOW_VERT_CNTL         0x02dc#define R128_BASE_CODE                    0x0f0b#define R128_BIOS_0_SCRATCH               0x0010#define R128_BIOS_1_SCRATCH               0x0014#define R128_BIOS_2_SCRATCH               0x0018#define R128_BIOS_3_SCRATCH               0x001c#define R128_BIOS_4_SCRATCH               0x0020#define R128_BIOS_5_SCRATCH               0x0024#       define R128_BIOS_DISPLAY_FP       (1 << 0)#       define R128_BIOS_DISPLAY_CRT      (2 << 0)#       define R128_BIOS_DISPLAY_FP_CRT   (3 << 0)/* R128_DUALHEAD is just a flag for the driver;   it doesn't actually correspond to any bits  */#	define R128_DUALHEAD		  4#define R128_BIOS_6_SCRATCH               0x0028#define R128_BIOS_7_SCRATCH               0x002c#define R128_BIOS_ROM                     0x0f30 /* PCI */#define R128_BIST                         0x0f0f /* PCI */#define R128_BM_CHUNK_0_VAL               0x0a18#       define R128_BM_PTR_FORCE_TO_PCI    (1 << 21)#       define R128_BM_PM4_RD_FORCE_TO_PCI (1 << 22)#       define R128_BM_GLOBAL_FORCE_TO_PCI (1 << 23)#define R128_BRUSH_DATA0                  0x1480#define R128_BRUSH_DATA1                  0x1484#define R128_BRUSH_DATA10                 0x14a8#define R128_BRUSH_DATA11                 0x14ac#define R128_BRUSH_DATA12                 0x14b0#define R128_BRUSH_DATA13                 0x14b4#define R128_BRUSH_DATA14                 0x14b8#define R128_BRUSH_DATA15                 0x14bc#define R128_BRUSH_DATA16                 0x14c0#define R128_BRUSH_DATA17                 0x14c4#define R128_BRUSH_DATA18                 0x14c8#define R128_BRUSH_DATA19                 0x14cc#define R128_BRUSH_DATA2                  0x1488#define R128_BRUSH_DATA20                 0x14d0#define R128_BRUSH_DATA21                 0x14d4#define R128_BRUSH_DATA22                 0x14d8#define R128_BRUSH_DATA23                 0x14dc#define R128_BRUSH_DATA24                 0x14e0#define R128_BRUSH_DATA25                 0x14e4#define R128_BRUSH_DATA26                 0x14e8#define R128_BRUSH_DATA27                 0x14ec#define R128_BRUSH_DATA28                 0x14f0#define R128_BRUSH_DATA29                 0x14f4#define R128_BRUSH_DATA3                  0x148c#define R128_BRUSH_DATA30                 0x14f8#define R128_BRUSH_DATA31                 0x14fc#define R128_BRUSH_DATA32                 0x1500#define R128_BRUSH_DATA33                 0x1504#define R128_BRUSH_DATA34                 0x1508#define R128_BRUSH_DATA35                 0x150c#define R128_BRUSH_DATA36                 0x1510#define R128_BRUSH_DATA37                 0x1514#define R128_BRUSH_DATA38                 0x1518#define R128_BRUSH_DATA39                 0x151c#define R128_BRUSH_DATA4                  0x1490#define R128_BRUSH_DATA40                 0x1520#define R128_BRUSH_DATA41                 0x1524#define R128_BRUSH_DATA42                 0x1528#define R128_BRUSH_DATA43                 0x152c#define R128_BRUSH_DATA44                 0x1530#define R128_BRUSH_DATA45                 0x1534#define R128_BRUSH_DATA46                 0x1538#define R128_BRUSH_DATA47                 0x153c#define R128_BRUSH_DATA48                 0x1540#define R128_BRUSH_DATA49                 0x1544#define R128_BRUSH_DATA5                  0x1494#define R128_BRUSH_DATA50                 0x1548#define R128_BRUSH_DATA51                 0x154c#define R128_BRUSH_DATA52                 0x1550#define R128_BRUSH_DATA53                 0x1554#define R128_BRUSH_DATA54                 0x1558#define R128_BRUSH_DATA55                 0x155c#define R128_BRUSH_DATA56                 0x1560#define R128_BRUSH_DATA57                 0x1564#define R128_BRUSH_DATA58                 0x1568#define R128_BRUSH_DATA59                 0x156c#define R128_BRUSH_DATA6                  0x1498#define R128_BRUSH_DATA60                 0x1570#define R128_BRUSH_DATA61                 0x1574