?? atiregs.h
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#define MEM_INSTALLED 0x0060u /* Mach8 */#define ROM_ENA 0x0080u /* Mach8 */#define ROM_PAGE_ENA 0x0100u /* Mach8 */#define ROM_LOCATION 0xfe00u /* Mach8 */#define _8514_ONLY 0x0001u /* Mach32 */#define BUS_TYPE 0x000eu /* Mach32 */#define ISA_16_BIT 0x0000u /* Mach32 */#define EISA 0x0002u /* Mach32 */#define MICRO_C_16_BIT 0x0004u /* Mach32 */#define MICRO_C_8_BIT 0x0006u /* Mach32 */#define LOCAL_386SX 0x0008u /* Mach32 */#define LOCAL_386DX 0x000au /* Mach32 */#define LOCAL_486 0x000cu /* Mach32 */#define PCI 0x000eu /* Mach32 */#define MEM_TYPE 0x0070u /* Mach32 */#define CHIP_DIS 0x0080u /* Mach32 */#define TST_VCTR_ENA 0x0100u /* Mach32 */#define DACTYPE 0x0e00u /* Mach32 */#define MC_ADR_DECODE 0x1000u /* Mach32 */#define CARD_ID 0xe000u /* Mach32 */#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */#define CONFIG_STATUS_2 0x16eeu /* Read */#define SHARE_CLOCK 0x0001u /* Mach8 */#define HIRES_BOOT 0x0002u /* Mach8 */#define EPROM_16_ENA 0x0004u /* Mach8 */#define WRITE_PER_BIT 0x0008u /* Mach8 */#define FLASH_ENA 0x0010u /* Mach8 */#define SLOW_SEQ_EN 0x0001u /* Mach32 */#define MEM_ADDR_DIS 0x0002u /* Mach32 */#define ISA_16_ENA 0x0004u /* Mach32 */#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */#define LOCAL_DAC_EN 0x0100u /* Mach32 */#define LOCAL_RDY_EN 0x0200u /* Mach32 */#define EEPROM_ADR_SEL 0x0400u /* Mach32 */#define GE_STRAP_SEL 0x0800u /* Mach32 */#define VESA_RDY 0x1000u /* Mach32 */#define Z4GB 0x2000u /* Mach32 */#define LOC2_MDRAM 0x4000u /* Mach32 */#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */#define PCI_CNTL 0x22eeu /* Mach32-PCI */#define CRT_PITCH 0x26eeu /* Write */#define CRT_OFFSET_LO 0x2aeeu /* Write */#define CRT_OFFSET_HI 0x2eeeu /* Write */#define LOCAL_CNTL 0x32eeu /* Mach32 */#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */#define MISC_OPTIONS 0x36eeu /* Mach32 */#define W_STATE_ENA 0x0000u /* Mach32 */#define HOST_8_ENA 0x0001u /* Mach32 */#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */#define MEM_SIZE_512K 0x0000u /* Mach32 */#define MEM_SIZE_1M 0x0004u /* Mach32 */#define MEM_SIZE_2M 0x0008u /* Mach32 */#define MEM_SIZE_4M 0x000cu /* Mach32 */#define DISABLE_VGA 0x0010u /* Mach32 */#define _16_BIT_IO 0x0020u /* Mach32 */#define DISABLE_DAC 0x0040u /* Mach32 */#define DLY_LATCH_ENA 0x0080u /* Mach32 */#define TEST_MODE 0x0100u /* Mach32 */#define BLK_WR_ENA 0x0400u /* Mach32 */#define _64_DRAW_ENA 0x0800u /* Mach32 */#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */#define MEM_BNDRY 0x42eeu /* Mach32 */#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */#define MEM_BNDRY_ENA 0x0010u /* Mach32 */#define SHADOW_CTL 0x46eeu /* Write */#define CLOCK_SEL 0x4aeeu/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */#define VFIFO_DEPTH_1 0x0100u /* Mach32 */#define VFIFO_DEPTH_2 0x0200u /* Mach32 */#define VFIFO_DEPTH_3 0x0300u /* Mach32 */#define VFIFO_DEPTH_4 0x0400u /* Mach32 */#define VFIFO_DEPTH_5 0x0500u /* Mach32 */#define VFIFO_DEPTH_6 0x0600u /* Mach32 */#define VFIFO_DEPTH_7 0x0700u /* Mach32 */#define VFIFO_DEPTH_8 0x0800u /* Mach32 */#define VFIFO_DEPTH_9 0x0900u /* Mach32 */#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */#define COMPOSITE_SYNC 0x1000u/* ? 0x4eeeu */#define ROM_ADDR_1 0x52eeu#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 *//* ? 0xff80u */ /* Mach32 */#define ROM_ADDR_2 0x56eeu /* Sick ... */#define SHADOW_SET 0x5aeeu /* Write */#define MEM_CFG 0x5eeeu /* Mach32 */#define MEM_APERT_SEL 0x0003u /* Mach32 */#define MEM_APERT_PAGE 0x000cu /* Mach32 */#define MEM_APERT_LOC 0xfff0u /* Mach32 */#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */#define MAX_WAITSTATES 0x6aeeu#define GE_OFFSET_LO 0x6eeeu /* Write */#define BOUNDS_LEFT 0x72eeu /* Read */#define GE_OFFSET_HI 0x72eeu /* Write */#define BOUNDS_TOP 0x76eeu /* Read */#define GE_PITCH 0x76eeu /* Write */#define BOUNDS_RIGHT 0x7aeeu /* Read */#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */#define MONITOR_ALIAS 0x0007u /* Mach32 *//* MONITOR_? 0x0000u */ /* Mach32 */#define MONITOR_8507 0x0001u /* Mach32 */#define MONITOR_8514 0x0002u /* Mach32 *//* MONITOR_? 0x0003u */ /* Mach32 *//* MONITOR_? 0x0004u */ /* Mach32 */#define MONITOR_8503 0x0005u /* Mach32 */#define MONITOR_8512 0x0006u /* Mach32 */#define MONITOR_8513 0x0006u /* Mach32 */#define MONITOR_NONE 0x0007u /* Mach32 */#define ALIAS_ENA 0x0008u /* Mach32 */#define PIXEL_WIDTH_4 0x0000u /* Mach32 */#define PIXEL_WIDTH_8 0x0010u /* Mach32 */#define PIXEL_WIDTH_16 0x0020u /* Mach32 */#define PIXEL_WIDTH_24 0x0030u /* Mach32 */#define RGB16_555 0x0000u /* Mach32 */#define RGB16_565 0x0040u /* Mach32 */#define RGB16_655 0x0080u /* Mach32 */#define RGB16_664 0x00c0u /* Mach32 */#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */#define RGB24 0x0000u /* Mach32 */#define RGBx24 0x0200u /* Mach32 */#define BGR24 0x0400u /* Mach32 */#define xBGR24 0x0600u /* Mach32 */#define DAC_8_BIT_EN 0x4000u /* Mach32 */#define ORDER_16BPP_565 RGB16_565 /* Mach32 */#define BOUNDS_BOTTOM 0x7eeeu /* Read */#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */#define PATT_DATA_INDEX 0x82eeu/* ? 0x86eeu *//* ? 0x8aeeu */#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */#define PATT_DATA 0x8eeeu /* Write */#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */#define BRES_COUNT 0x96eeu#define EXT_FIFO_STATUS 0x9aeeu /* Read */#define LINEDRAW_INDEX 0x9aeeu /* Write *//* ? 0x9eeeu */#define LINEDRAW_OPT 0xa2eeu#define BOUNDS_RESET 0x0100u#define CLIP_MODE_0 0x0000u /* Clip exception disabled */#define CLIP_MODE_1 0x0200u /* Line segments */#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */#define CLIP_MODE_3 0x0600u /* Patterned lines */#define DEST_X_START 0xa6eeu /* Write */#define DEST_X_END 0xaaeeu /* Write */#define DEST_Y_END 0xaeeeu /* Write */#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */#define SRC_X_STRT 0xb2eeu /* Write */#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */#define ALU_BG_FN 0xb6eeu /* Write */#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */#define ALU_FG_FN 0xbaeeu /* Write */#define SRC_X_END 0xbeeeu /* Write */#define R_V_TOTAL 0xc2eeu /* Read */#define SRC_Y_DIR 0xc2eeu /* Write */#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */#define EXT_SHORT_STROKE 0xc6eeu /* Write */#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */#define SCAN_X 0xcaeeu /* Write */#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */#define DP_CONFIG 0xceeeu /* Write */#define READ_WRITE 0x0001u#define DATA_WIDTH 0x0200u#define DATA_ORDER 0x1000u#define FG_COLOR_SRC_FG 0x2000u#define FG_COLOR_SRC_BLIT 0x6000u#define R_V_SYNC_WID 0xd2eeu /* Read */#define PATT_LENGTH 0xd2eeu /* Write */#define PATT_INDEX 0xd6eeu /* Write */#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */#define EXT_SCISSOR_L 0xdaeeu /* Write */#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */#define EXT_SCISSOR_T 0xdeeeu /* Write */#define EXT_SCISSOR_R 0xe2eeu /* Write */#define EXT_SCISSOR_B 0xe6eeu /* Write *//* ? 0xeaeeu */#define DEST_COMP_FN 0xeeeeu /* Write */#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 *//* ? 0xf6eeu */#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */#define CHIP_CODE_0 0x001fu /* Mach32 */#define CHIP_CODE_1 0x03e0u /* Mach32 */#define CHIP_CLASS 0x0c00u /* Mach32 */#define CHIP_REV 0xf000u /* Mach32 */#define LINEDRAW 0xfeeeu /* Write *//* ATI Mach64 register definitions */#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u)#define CRTC_H_TOTAL 0x000001fful/* ? 0x0000fe00ul */#define CRTC_H_DISP 0x01ff0000ul/* ? 0xfe000000ul */#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u)#define CRTC_H_SYNC_STRT 0x000000fful#define CRTC_H_SYNC_DLY 0x00000700ul/* ? 0x00000800ul */#define CRTC_H_SYNC_STRT_HI 0x00001000ul/* ? 0x0000e000ul */#define CRTC_H_SYNC_WID 0x001f0000ul#define CRTC_H_SYNC_POL 0x00200000ul/* ? 0xffc00000ul */#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u)#define CRTC_V_TOTAL 0x000007fful/* ? 0x0000f800ul */#define CRTC_V_DISP 0x07ff0000ul/* ? 0xf8000000ul */#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u)#define CRTC_V_SYNC_STRT 0x000007fful/* ? 0x0000f800ul */#define CRTC_V_SYNC_WID 0x001f0000ul#define CRTC_V_SYNC_END_VGA 0x000f0000ul#define CRTC_V_SYNC_POL 0x00200000ul/* ? 0xffc00000ul */#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u)#define CRTC_VLINE 0x000007fful/* ? 0x0000f800ul */#define CRTC_CRNT_VLINE 0x07ff0000ul/* ? 0xf8000000ul */#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u)#define CRTC_OFFSET 0x000ffffful#define CRTC_OFFSET_VGA 0x0003fffful#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL *//* ? 0x00200000ul */#define CRTC_PITCH 0xffc00000ul#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u)#define CRTC_VBLANK 0x00000001ul#define CRTC_VBLANK_INT_EN 0x00000002ul#define CRTC_VBLANK_INT 0x00000004ul#define CRTC_VLINE_INT_EN 0x00000008ul#define CRTC_VLINE_INT 0x00000010ul#define CRTC_VLINE_SYNC 0x00000020ul#define CRTC_FRAME 0x00000040ul#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */#define CRTC_I2C_INT 0x00000400ul /* GTPro */#define CRTC2_VBLANK 0x00000800ul /* LTPro */#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */#define CRTC_INT_ENS /* *** UPDATE ME *** */ \ ( \ CRTC_VBLANK_INT_EN | \ CRTC_VLINE_INT_EN | \ CRTC_SNAPSHOT_INT_EN | \ CRTC_I2C_INT_EN | \ CRTC2_VBLANK_INT_EN | \ CRTC2_VLINE_INT_EN | \ CRTC_CAPBUF0_INT_EN | \ CRTC_CAPBUF1_INT_EN | \ CRTC_OVERLAY_EOF_INT_EN | \ CRTC_ONESHOT_CAP_INT_EN | \ CRTC_BUSMASTER_EOL_INT_EN | \ CRTC_GP_INT_EN | \ CRTC_SNAPSHOT2_INT_EN | \ 0 \ )#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ ( \ CRTC_VBLANK_INT | \ CRTC_VLINE_INT | \ CRTC_SNAPSHOT_INT | \ CRTC_I2C_INT | \ CRTC2_VBLANK_INT | \ CRTC2_VLINE_INT | \ CRTC_CAPBUF0_INT | \ CRTC_CAPBUF1_INT | \ CRTC_OVERLAY_EOF_INT | \ CRTC_ONESHOT_CAP_INT | \ CRTC_BUSMASTER_EOL_INT | \ CRTC_GP_INT | \ CRTC_SNAPSHOT2_INT | \ CRTC_VBLANK_BIT2_INT | \ 0 \ )#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u)#define CRTC_DBL_SCAN_EN 0x00000001ul#define CRTC_INTERLACE_EN 0x00000002ul#define CRTC_HSYNC_DIS 0x00000004ul#define CRTC_VSYNC_DIS 0x00000008ul#define CRTC_CSYNC_EN 0x00000010ul#define CRTC_PIX_BY_2_EN 0x00000020ul#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */#define CRTC_DISPLAY_DIS 0x00000040ul#define CRTC_VGA_XOVERSCAN 0x00000080ul#define CRTC_PIX_WIDTH 0x00000700ul#define CRTC_BYTE_PIX_ORDER 0x00000800ul#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */#define CRTC_FIFO_LWM 0x000f0000ul#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */?? 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