pATIHW->genmo |= 0x80U;    }    else    {        pMode->Flags &= ~(V_PHSYNC | V_NHSYNC | V_PVSYNC | V_NVSYNC);        if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0))            VDisplay = pATI->LCDVertical;        else            VDisplay = pMode->CrtcVDisplay;        if (VDisplay < 400)        {            pMode->Flags |= V_PHSYNC | V_NVSYNC;            pATIHW->genmo |= 0x80U;        }        else if (VDisplay < 480)        {            pMode->Flags |= V_NHSYNC | V_PVSYNC;            pATIHW->genmo |= 0x40U;        }        else if (VDisplay < 768)        {            pMode->Flags |= V_NHSYNC | V_NVSYNC;            pATIHW->genmo |= 0xC0U;        }        else        {            pMode->Flags |= V_PHSYNC | V_PVSYNC;        }    }    /* Adjust for interlaced modes */    if ((pMode->Flags & V_INTERLACE) && (pATI->Chip < ATI_CHIP_264CT))    {        pMode->CrtcVDisplay >>= 1;        pMode->CrtcVBlankStart >>= 1;        pMode->CrtcVSyncStart >>= 1;        pMode->CrtcVSyncEnd >>= 1;        pMode->CrtcVBlankEnd >>= 1;        pMode->CrtcVTotal >>= 1;    }    if (pMode->CrtcVTotal > 1024)    {        pATIHW->crt[23] |= 0x04U;        pMode->CrtcVDisplay >>= 1;        pMode->CrtcVBlankStart >>= 1;        pMode->CrtcVSyncStart >>= 1;        pMode->CrtcVSyncEnd >>= 1;        pMode->CrtcVBlankEnd >>= 1;        pMode->CrtcVTotal >>= 1;    }    else    {        pATIHW->crt[23] &= ~0x04U;    }    pMode->CrtcVDisplay--;    if (pATI->Chip == ATI_CHIP_18800)        pMode->CrtcVBlankStart++;    else        pMode->CrtcVBlankStart--;    if (pATI->LCDPanelID >= 0)    {        pMode->CrtcVSyncStart--;        pMode->CrtcVSyncEnd--;    }    pMode->CrtcVBlankEnd--;    if (pATI->Chip < ATI_CHIP_264CT)        pMode->CrtcVBlankEnd--;    pMode->CrtcVTotal -= 2;    pMode->CrtcVAdjusted = TRUE;        /* Redundant */    /* Check sync pulse width */    Index = pMode->CrtcVSyncEnd - pMode->CrtcVSyncStart - 0x0F;    if (Index > 0)    {        pMode->CrtcVSyncStart += Index / 2;        pMode->CrtcVSyncEnd = pMode->CrtcVSyncStart + 0x0F;    }    /* Check blank pulse width */    Index = pMode->CrtcVBlankEnd - pMode->CrtcVBlankStart - 0x00FF;    if (Index > 0)    {        if ((pMode->CrtcVBlankEnd - Index) > pMode->CrtcVSyncEnd)        {            pMode->CrtcVBlankStart += Index / 2;            if (pMode->CrtcVBlankStart >= pMode->CrtcVSyncStart)                pMode->CrtcVBlankStart = pMode->CrtcVSyncStart - 1;            pMode->CrtcVBlankEnd = pMode->CrtcVBlankStart + 0x00FF;        }        else        {            Index -= 0x0100;            if (Index > 0)            {                pMode->CrtcVBlankStart += Index / 2;                if (pMode->CrtcVBlankStart >= pMode->CrtcVSyncStart)                    pMode->CrtcVBlankStart = pMode->CrtcVSyncStart - 1;                pMode->CrtcVBlankEnd = pMode->CrtcVBlankStart + 0x01FF;            }        }    }    /* Set up sequencer register values */    if (pMode->Flags & V_CLKDIV2)        pATIHW->seq[1] = 0x09U;    else        pATIHW->seq[1] = 0x01U;    /* Set up CRTC register values */    pATIHW->crt[0] = pMode->CrtcHTotal;    pATIHW->crt[1] = pMode->CrtcHDisplay;    pATIHW->crt[2] = pMode->CrtcHBlankStart;    pATIHW->crt[3] = (pMode->CrtcHBlankEnd & 0x1FU) | 0x80U;    Index = ((pMode->CrtcHSkew << 2) + 0x10U) & ~0x1FU;    if (Index < 0x0080)        pATIHW->crt[3] |= Index;    pATIHW->crt[4] = pMode->CrtcHSyncStart;    pATIHW->crt[5] = ((pMode->CrtcHBlankEnd & 0x20U) << 2) |                     ((pMode->CrtcHSyncEnd & 0x1FU)      );    pATIHW->crt[6] = pMode->CrtcVTotal & 0xFFU;    pATIHW->crt[7] = ((pMode->CrtcVTotal & 0x0100U) >> 8) |                     ((pMode->CrtcVDisplay & 0x0100U) >> 7) |                     ((pMode->CrtcVSyncStart & 0x0100U) >> 6) |                     ((pMode->CrtcVBlankStart & 0x0100U) >> 5) |                     0x10U |                     ((pMode->CrtcVTotal & 0x0200U) >> 4) |                     ((pMode->CrtcVDisplay & 0x0200U) >> 3) |                     ((pMode->CrtcVSyncStart & 0x0200U) >> 2);    pATIHW->crt[9] = ((pMode->CrtcVBlankStart & 0x0200U) >> 4) | 0x40U;    /*     * Doublescanned modes are missing the top scanline.  Convert     * doublescanning to multiscanning, using the doublescan bit only as a last     * resort.     */    if ((Index = pMode->VScan) <= 0)        Index = 1;    if (pMode->Flags & V_DBLSCAN)        Index <<= 1;    Index--;    pATIHW->crt[9] |= (Index & 0x1FU) | ((Index & 0x20U) << 2);    pATIHW->crt[16] = pMode->CrtcVSyncStart & 0xFFU;    pATIHW->crt[17] = (pMode->CrtcVSyncEnd & 0x0FU) | 0x20U;    pATIHW->crt[18] = pMode->CrtcVDisplay & 0xFFU;    pATIHW->crt[21] = pMode->CrtcVBlankStart & 0xFFU;    pATIHW->crt[22] = pMode->CrtcVBlankEnd & 0xFFU;}/* * ATIVGASet -- * * This function is called to load the VGA portion of a video state. */voidATIVGASet(    ATIPtr      pATI,    ATIHWPtr    pATIHW){    int Index;    /* Set VGA I/O base */    ATISetVGAIOBase(pATI, pATIHW->genmo);    /* Load miscellaneous output register */    outb(GENMO, pATIHW->genmo);    /* Load sequencer in reverse index order;  this also ends its reset */    for (Index = NumberOf(pATIHW->seq);  --Index >= 0;  )        PutReg(SEQX, Index, pATIHW->seq[Index]);    /* Load CRTC registers */    for (Index = 0;  Index < NumberOf(pATIHW->crt);  Index++)        PutReg(CRTX(pATI->CPIO_VGABase), Index, pATIHW->crt[Index]);    /* Load attribute controller registers */    for (Index = 0;  Index < NumberOf(pATIHW->attr);  Index++)    {        (void)inb(GENS1(pATI->CPIO_VGABase));   /* Reset flip-flop & delay */        outb(ATTRX, Index);        outb(ATTRX, pATIHW->attr[Index]);    }    /* Load graphics controller registers */    for (Index = 0;  Index < NumberOf(pATIHW->gra);  Index++)        PutReg(GRAX, Index, pATIHW->gra[Index]);}/* * ATIVGASaveScreen -- * * This function blanks or unblanks a VGA screen. */voidATIVGASaveScreen(    ATIPtr pATI,    int    Mode){    (void)inb(GENS1(pATI->CPIO_VGABase));       /* Reset flip-flop */    switch (Mode)    {        case SCREEN_SAVER_OFF:        case SCREEN_SAVER_FORCER:            outb(ATTRX, 0x20U);                /* Turn PAS on */            break;        case SCREEN_SAVER_ON:        case SCREEN_SAVER_CYCLE:            outb(ATTRX, 0x00U);                /* Turn PAS off */            break;        default:            break;    }}/* * ATIVGASetDPMSMode -- * * This function sets a VGA's VESA Display Power Management Signaling mode. */voidATIVGASetDPMSMode(    ATIPtr pATI,    int    DPMSMode){    CARD8 seq1, crt17;    switch (DPMSMode)    {        case DPMSModeOn:        /* HSync on, VSync on */            seq1 = 0x00U;            crt17 = 0x80U;            break;        case DPMSModeStandby:   /* HSync off, VSync on -- unsupported */            seq1 = 0x20U;            crt17 = 0x80U;            break;        case DPMSModeSuspend:   /* HSync on, VSync off -- unsupported */            seq1 = 0x20U;            crt17 = 0x80U;            break;        case DPMSModeOff:       /* HSync off, VSync off */            seq1 = 0x20U;            crt17 = 0x00U;            break;        default:                /* Muffle compiler */            return;    }    PutReg(SEQX, 0x00U, 0x01U); /* Start synchonous reset */    seq1 |= GetReg(SEQX, 0x01U) & ~0x20U;    PutReg(SEQX, 0x01U, seq1);    crt17 |= GetReg(CRTX(pATI->CPIO_VGABase), 0x17U) & ~0x80U;    usleep(10000);    PutReg(CRTX(pATI->CPIO_VGABase), 0x17U, crt17);    PutReg(SEQX, 0x01U, 0x03U); /* End synchonous reset */}#endif /* AVOID_CPIO */