/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c,v 1.21 2003/04/23 21:51:27 tsi Exp $ *//* * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission.  Marc Aurele La France makes no representations * about the suitability of this software for any purpose.  It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.  IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. *//* * Adapters prior to V5 use 4 crystals.  Adapters V5 and later use a clock * generator chip.  V3 and V4 adapters differ when it comes to choosing clock * frequencies. * * VGA Wonder V3/V4 Adapter Clock Frequencies * R E G I S T E R S * 1CE(*)    3C2     3C2    Frequency * B2h/BEh * Bit 6/4  Bit 3   Bit 2   (MHz) * ------- ------- -------  ------- *    0       0       0     50.000 *    0       0       1     56.644 *    0       1       0     Spare 1 *    0       1       1     44.900 *    1       0       0     44.900 *    1       0       1     50.000 *    1       1       0     Spare 2 *    1       1       1     36.000 * * (*):  V3 uses index B2h, bit 6;  V4 uses index BEh, bit 4 * * V5, PLUS, XL and XL24 usually have an ATI 18810 clock generator chip, but * some have an ATI 18811-0, and it's quite conceivable that some exist with * ATI 18811-1's or ATI 18811-2's.  Mach32 adapters are known to use any one of * these clock generators.  Mach32 adapters also use a different dot clock * ordering.  ATI says there is no reliable way for the driver to determine * which clock generator is on the adapter, but this driver will do its best to * do so anyway. * * VGA Wonder V5/PLUS/XL/XL24 Clock Frequencies * R E G I S T E R S *   1CE     1CE     3C2     3C2    Frequency *   B9h     BEh                     (MHz)   18811-0  18811-1 *  Bit 1   Bit 4   Bit 3   Bit 2    18810   18812-0  18811-2  (*5) * ------- ------- ------- -------  -------  -------  -------  ------- *    0       0       0       0      30.240   30.240  135.000   75.000 *    0       0       0       1      32.000   32.000   32.000   77.500 *    0       0       1       0      37.500  110.000  110.000   80.000 *    0       0       1       1      39.000   80.000   80.000   90.000 *    0       1       0       0      42.954   42.954  100.000   25.175 *    0       1       0       1      48.771   48.771  126.000   28.322 *    0       1       1       0        (*1)   92.400   92.400   31.500 *    0       1       1       1      36.000   36.000   36.000   36.000 *    1       0       0       0      40.000   39.910   39.910  100.000 *    1       0       0       1        (*4)   44.900   44.900  110.000 *    1       0       1       0      75.000   75.000   75.000  126.000 *    1       0       1       1      65.000   65.000   65.000  135.000 *    1       1       0       0      50.350   50.350   50.350   40.000 *    1       1       0       1      56.640   56.640   56.640   44.900 *    1       1       1       0        (*2)     (*3)     (*3)   50.000 *    1       1       1       1      44.900   44.900   44.900   65.000 * * (*1) External 0 (supposedly 16.657 Mhz) * (*2) External 1 (supposedly 28.322 MHz) * (*3) This setting doesn't seem to generate anything * (*4) This setting is documented to be 56.644 MHz, but something close to 82 *      MHz has also been encountered. * (*5) This setting is for Dell OmniPlex 590 systems, with a 68800AX on the *      motherboard, along with an AT&T21C498 DAC (which is reported as an *      STG1700) and ICS2494AM clock generator (a.k.a. ATI 18811-?). * * Mach32 Clock Frequencies * R E G I S T E R S *   1CE     1CE     3C2     3C2    Frequency *   B9h     BEh                     (MHz)   18811-0  18811-1 *  Bit 1   Bit 4   Bit 3   Bit 2    18810   18812-0  18811-2  (*5) * ------- ------- ------- -------  -------  -------  -------  ------- *    0       0       0       0      42.954   42.954  100.000   25.175 *    0       0       0       1      48.771   48.771  126.000   28.322 *    0       0       1       0        (*1)   92.400   92.400   31.500 *    0       0       1       1      36.000   36.000   36.000   36.000 *    0       1       0       0      30.240   30.240  135.000   75.000 *    0       1       0       1      32.000   32.000   32.000   77.500 *    0       1       1       0      37.500  110.000  110.000   80.000 *    0       1       1       1      39.000   80.000   80.000   90.000 *    1       0       0       0      50.350   50.350   50.350   40.000 *    1       0       0       1      56.640   56.640   56.640   44.900 *    1       0       1       0        (*2)     (*3)     (*3)   50.000 *    1       0       1       1      44.900   44.900   44.900   65.000 *    1       1       0       0      40.000   39.910   39.910  100.000 *    1       1       0       1        (*4)   44.900   44.900  110.000 *    1       1       1       0      75.000   75.000   75.000  126.000 *    1       1       1       1      65.000   65.000   65.000  135.000 * * (*1) External 0 (supposedly 16.657 Mhz) * (*2) External 1 (supposedly 28.322 MHz) * (*3) This setting doesn't seem to generate anything * (*4) This setting is documented to be 56.644 MHz, but something close to 82 *      MHz has also been encountered. * (*5) This setting is for Dell OmniPlex 590 systems, with a 68800AX on the *      motherboard, along with an AT&T21C498 DAC (which is reported as an *      STG1700) and ICS2494AM clock generator (a.k.a. ATI 18811-?). * * Note that, to reduce confusion, this driver masks out the different clock * ordering. * * For all adapters, these frequencies can be divided by 1 or 2.  For all * adapters, except Mach32's and Mach64's, frequencies can also be divided by 3 * or 4. * *      Register 1CE, index B8h *       Bit 7    Bit 6 *      -------  ------- *         0        0           Divide by 1 *         0        1           Divide by 2 *         1        0           Divide by 3 *         1        1           Divide by 4 * * With respect to clocks, Mach64's are entirely different animals. * * The oldest Mach64's use one of the non-programmable clock generators * described above.  In this case, the driver will handle clocks in much the * same way as it would for a Mach32. * * All other Mach64 adapters use a programmable clock generator.  BIOS * initialisation programmes an initial set of frequencies.  Two of these are * reserved to allow for the setting of modes that do not use a frequency from * this initial set.  One of these reserved slots is used by the BIOS mode set * routine, the other by the particular accelerated driver used (MS-Windows, * AutoCAD, etc.).  The slots reserved in this way are dependent on the * particular clock generator used by the adapter. * * If the driver does not support the adapter's clock generator, it will try to * match the (probed or specified) clocks to one of the following sets. * * Mach64 Clock Frequencies for unsupported programmable clock generators * R E G I S T E R S *   1CE     1CE     3C2     3C2    Frequency *   B9h     BEh                     (MHz) *  Bit 1   Bit 4   Bit 3   Bit 2    Set 1    Set 2    Set 3 * ------- ------- ------- -------  -------  -------  ------- *    0       0       0       0      50.350   25.180   25.180 *    0       0       0       1      56.640   28.320   28.320 *    0       0       1       0      63.000   31.500    0.000 *    0       0       1       1      72.000   36.000    0.000 *    0       1       0       0       0.000    0.000    0.000 *    0       1       0       1     110.000  110.000    0.000 *    0       1       1       0     126.000  126.000    0.000 *    0       1       1       1     135.000  135.000    0.000 *    1       0       0       0      40.000   40.000    0.000 *    1       0       0       1      44.900   44.900    0.000 *    1       0       1       0      49.500   49.500    0.000 *    1       0       1       1      50.000   50.000    0.000 *    1       1       0       0       0.000    0.000    0.000 *    1       1       0       1      80.000   80.000    0.000 *    1       1       1       0      75.000   75.000    0.000 *    1       1       1       1      65.000   65.000    0.000 * * The driver will never select a setting of 0.000 MHz.  The above comments on * clock ordering and clock divider apply here also. * * For all supported programmable clock generators, the driver will ignore any * XF86Config clock line and programme, as needed, the clock number reserved by * the BIOS for accelerated drivers.  The driver's mode initialisation routine * finds integers N, M and D such that * *             N *      R * -------  MHz *           M * D * * best approximates the mode's clock frequency, where R is the crystal- * generated reference frequency (usually 14.318 MHz).  D is a power of 2 * except for those integrated controllers that also offer odd dividers. * Different clock generators have different restrictions on the value N, M and * D can assume.  The driver contains an internal table to record these * restrictions (among other things).  The resulting values of N, M and D are * then encoded in a generator-specific way and used to programme the clock. * The Mach64's clock divider is not used in this case. */#ifdef HAVE_CONFIG_H#include "config.h"#endif#include <stdlib.h>#include "ati.h"#include "atiadapter.h"#include "atichip.h"#include "atidac.h"#include "atidsp.h"#include "atimach64io.h"#include "atimode.h"#include "atiwonderio.h"/* * Definitions related to non-programmable clock generators. */const char *ATIClockNames[] ={    "unknown",    "IBM VGA compatible",    "crystals",    "ATI 18810 or similar",    "ATI 18811-0 or similar",    "ATI 18811-1 or similar",    "ICS 2494-AM or similar",    "Programmable (BIOS setting 1)",    "Programmable (BIOS setting 2)",    "Programmable (BIOS setting 3)"};/* * Definitions related to programmable clock generators. */static CARD16 ATIPostDividers[] = {1, 2, 4, 8, 16, 32, 64, 128},              ATI264xTPostDividers[] = {1, 2, 4, 8, 3, 0, 6, 12};ClockRec ATIClockDescriptors[] ={    {          0,   0,   0, 1, 1,          1,   1,   0,          0, NULL,        "Non-programmable"    },    {        257, 512, 257, 1, 1,         46,  46,   0,          4, ATIPostDividers,        "ATI 18818 or ICS 2595 or similar"    },    {          2, 129,   2, 1, 1,          8,  14,   2,          8, ATIPostDividers,        "SGS-Thompson 1703 or similar"    },    {         16, 263,   8, 8, 9,          4,  12,   2,          4, ATIPostDividers,        "Chrontel 8398 or similar"    },    {          2, 255,   0, 1, 1,         45,  45,   0,          4, ATI264xTPostDividers,        "Internal"    },    {          2, 257,   2, 1, 1,          2,  32,   2,          4, ATIPostDividers,        "AT&T 20C408 or similar"    },    {         65, 128,  65, 1, 1,          2,  14,   0,          4, ATIPostDividers,        "IBM RGB 514 or similar"    }};/* * XF86Config clocks line that start with the following will either be rejected * for ATI adapters, or accepted for non-ATI adapters. */static const intATIVGAClocks[] ={     25175,  28322,        -1};/* * The driver will attempt to match fixed clocks to one of the following * specifications. */static const intATICrystalFrequencies[] ={     50000,  56644,      0,  44900,  44900,  50000,      0,  36000,        -1},ATI18810Frequencies[] ={     30240,  32000,  37500,  39000,  42954,  48771,      0,  36000,     40000,      0,  75000,  65000,  50350,  56640,      0,  44900},ATI188110Frequencies[] ={     30240,  32000, 110000,  80000,  42954,  48771,  92400,  36000,     39910,  44900,  75000,  65000,  50350,  56640,      0,  44900},ATI188111Frequencies[] ={    135000,  32000, 110000,  80000, 100000, 126000,  92400,  36000,     39910,  44900,  75000,  65000,  50350,  56640,      0,  44900},ATI2494AMFrequencies[] ={     75000,  77500,  80000,  90000,  25175,  28322,  31500,  36000,    100000, 110000, 126000, 135000,  40000,  44900,  50000,  65000},ATIMach64AFrequencies[] ={         0, 110000, 126000, 135000,  50350,  56640,  63000,  72000,         0,  80000,  75000,  65000,  40000,  44900,  49500,  50000},ATIMach64BFrequencies[] ={         0, 110000, 126000, 135000,  25180,  28320,  31500,  36000,         0,  80000,  75000,  65000,  40000,  44900,  49500,  50000},ATIMach64CFrequencies[] ={         0,      0,      0,      0,  25180,  28320,      0,      0,         0,      0,      0,      0,      0,      0,      0,      0},*SpecificationClockLine[] ={    NULL,    ATIVGAClocks,    ATICrystalFrequencies,    ATI18810Frequencies,    ATI188110Frequencies,    ATI188111Frequencies,    ATI2494AMFrequencies,    ATIMach64AFrequencies,    ATIMach64BFrequencies,    ATIMach64CFrequencies,    NULL};/* * The driver will reject XF86Config clocks lines that start with, or are an * initial subset of, one of the following. */static const intATIPre_2_1_1_Clocks_A[] =       /* Based on 18810 */{     18000,  22450,  25175,  28320,  36000,  44900,  50350,  56640,     30240,  32000,  37500,  39000,  40000,      0,  75000,  65000,        -1},ATIPre_2_1_1_Clocks_B[] =       /* Based on 18811-0 */{     18000,  22450,  25175,  28320,  36000,  44900,  50350,  56640,     30240,  32000, 110000,  80000,  39910,  44900,  75000,  65000,        -1},ATIPre_2_1_1_Clocks_C[] =       /* Based on 18811-1 (or -2) */{     18000,  22450,  25175,  28320,  36000,  44900,  50350,  56640,    135000,  32000, 110000,  80000,  39910,  44900,  75000,  65000,        -1},ATIPre_2_1_1_Clocks_D[] =       /* Based on ICS 2494AM */{     18000,  32500,  20000,  22450,  36000,  65000,  40000,  44900,     75000,  77500,  80000,  90000, 100000, 110000, 126000, 135000,        -1},ATIPre_2_1_1_Clocks_E[] =       /* Based on programmable setting 1 */{     36000,  25000,  20000,  22450,  72000,  50000,  40000,  44900,         0, 110000, 126000, 135000,      0,  80000,  75000,  65000,        -1},ATIPre_2_1_1_Clocks_F[] =       /* Based on programmable setting 2 */{     18000,  25000,  20000,  22450,  36000,  50000,  40000,  44900,         0, 110000, 126000, 135000,      0,  80000,  75000,  65000,        -1},*InvalidClockLine[] ={    NULL,    ATIVGAClocks,    ATIPre_2_1_1_Clocks_A,    ATIPre_2_1_1_Clocks_B,    ATIPre_2_1_1_Clocks_C,    ATIPre_2_1_1_Clocks_D,    ATIPre_2_1_1_Clocks_E,    ATIPre_2_1_1_Clocks_F,    NULL};/* * Clock maps. */