?? et21x130_i2c_et.asm
字號:
;--------------------------------------------------------
; C_Compiler for ETOMS MCU
; Target MCU: ET44M210
;--------------------------------------------------------
; .module ET21x130_I2C
;--------------------------------------------------------
; publics variables in this module
;--------------------------------------------------------
; .globl _I2C_RxTx_Data_H
; .globl _I2C_RxTx_Data_L
; .globl _I2C_RxTx_Data
; .globl _COUNTER_16
; .globl _I2C_Reg_Index_H
; .globl _I2C_Reg_Index_L
; .globl _I2C_Reg_Index
; .globl _I2CRegR8_L
; .globl _I2CRegR8_H
; .globl _I2CRegR8
; .globl _I2CRegR7_L
; .globl _I2CRegR7_H
; .globl _I2CRegR7
; .globl _I2CRegR6_L
; .globl _I2CRegR6_H
; .globl _I2CRegR6
; .globl _I2CRegR5_L
; .globl _I2CRegR5_H
; .globl _I2CRegR5
; .globl _I2CRegR4_L
; .globl _I2CRegR4_H
; .globl _I2CRegR4
; .globl _I2CRegR3_L
; .globl _I2CRegR3_H
; .globl _I2CRegR3
; .globl _I2CRegR2_L
; .globl _I2CRegR2_H
; .globl _I2CRegR2
; .globl _I2CRegR1_L
; .globl _I2CRegR1_H
; .globl _I2CRegR1
; .globl _I2CRegR0_L
; .globl _I2CRegR0_H
; .globl _I2CRegR0
; .globl _HostCommand4
; .globl _HostCommand3
; .globl _HostCommand2
; .globl _HostCommand1
; .globl _HostCommand0
; .globl _Sensor_Flag
; .globl _BackUp_IAP1
; .globl _BackUp_RAMBS1
; .globl _TestData
; .globl _TEMP_count
; .globl _ColLineCount
; .globl _YDummyCounter
; .globl _RowPixelCounter
; .globl _STOCK_Counter
; .globl _USB_FIFO_Bank
; .globl _FIFO_Stock
; .globl _RAW_Bank
; .globl _RAW_Address
; .globl _usb_byTemp
; .globl _nAddrBuf
; .globl _nTable
; .globl _nRomAdr
; .globl _nwLength
; .globl _nHwLength
; .globl _psz
; .globl _Reset_ET21x130
; .globl _Setup_ET21x130
; .globl _SetI2CReg
; .globl _GetI2CReg
; .globl _Check_SensorID
; .globl _Write_Register
; .globl _Read_Register
; .globl _I2C_Index
; .globl _I2C_Write
; .globl _I2C_Read
; .globl _I2C_IndexWrite
; .globl _I2C_DataWrite
; .globl _I2C_DataRead
; .globl _I2C_StopBit
; .globl _I2C_Write_SartBit
; .globl _I2C_Read_SartBit
;--------------------------------------------------------
; special function registers
_IAC0 EQU 0x00
_HPC EQU 0x01
_LPC EQU 0x02
_STTS EQU 0x03
_STATUS EQU 0x03
_RAMBS0 EQU 0x04
_ROMPS EQU 0x05
_IAP0 EQU 0x06
_INDP0 EQU 0x06
_RAMBS1 EQU 0x07
_IAP1 EQU 0x08
_INDP1 EQU 0x08
_IAC1 EQU 0x09
_INDR1 EQU 0x09
_IAPADR EQU 0x0a
_TBLPTR EQU 0x0b
_LTBL EQU 0x0b
_TBHPTR EQU 0x0c
_HTBL EQU 0x0c
_STKPTR EQU 0x0d
_RPTC EQU 0x0e
_PRC EQU 0x0f
_TCC EQU 0x10
_INTF EQU 0x11
_KWUPAIF EQU 0x12
_KWUPBIF EQU 0x13
_PORTA EQU 0x14
_PTA EQU 0x14
_PORTB EQU 0x15
_PTB EQU 0x15
_PORTC EQU 0x16
_PTC EQU 0x16
_PORTD EQU 0x17
_PTD EQU 0x17
_PORTE EQU 0x18
_PTE EQU 0x18
_PORTF EQU 0x19
_PTF EQU 0x19
_LFRC EQU 0x1a
_HFRC EQU 0x1b
_LFRCB EQU 0x1c
_SPIRB EQU 0x1d
_SPIWB EQU 0x1e
_ADDATAH EQU 0x1f
_ADDATAL EQU 0x20
_DT0L EQU 0x21
_DTOH EQU 0x22
_PRD0L EQU 0x23
_PRD0H EQU 0x24
_DL0L EQU 0x25
_DL0H EQU 0x26
_DT1L EQU 0x27
_DT1H EQU 0x28
_PRD1L EQU 0x29
_PRD1H EQU 0x2a
_DL1L EQU 0x2b
_DL1H EQU 0x2c
_PRIE EQU 0x80
_INTE EQU 0x81
_KWUAIE EQU 0x82
_KWUBIE EQU 0x83
_EINTED EQU 0x84
_SPIC EQU 0x85
_IOCA EQU 0x86
_IOCB EQU 0x87
_IOCC EQU 0x88
_IOCD EQU 0x89
_IOCE EQU 0x8a
_IOCF EQU 0x8b
_PUCA EQU 0x8c
_PUCB EQU 0x8d
_PUCC EQU 0x8e
_PUCD EQU 0x85
_PUCE EQU 0x90
_PUCF EQU 0x91
_ODCB EQU 0x92
_TCCC EQU 0x93
_FRCC EQU 0x94
_WDT_CON EQU 0x95
_ADCAIS EQU 0x96
_ADCCR EQU 0x97
_PWMCR EQU 0x98
_RFINTE EQU 0x99
_HbmRequestType EQU 0x80 ;Bank1 Source:180
_HbRequest EQU 0x81 ;Bank1 Source:181
_HwValueL EQU 0x82 ;Bank1 Source:182
_HwValueH EQU 0x83 ;Bank1 Source:183
_HwIndexL EQU 0x84 ;Bank1 Source:184
_HwIndexH EQU 0x85 ;Bank1 Source:185
_HwLengthL EQU 0x86 ;Bank1 Source:186
_HwLengthH EQU 0x87 ;Bank1 Source:187
_HTBLL EQU 0x88 ;Bank1 Source:188
_HROMADRL EQU 0x89 ;Bank1 Source:189
_HROMADRH EQU 0x8a ;Bank1 Source:18a
_A_INTERFACE EQU 0x8b ;Bank1 Source:18b
_TEMP_UREG EQU 0x8c ;Bank1 Source:18c
_PROTOCOL EQU 0x8d ;Bank1 Source:18d
_IDLE_TIMER EQU 0x8e ;Bank1 Source:18e
_USB_STATUS EQU 0x8f ;Bank1 Source:18f
_HUB_STATUS EQU 0x8f ;Bank1 Source:18f
_FC_STATUS EQU 0x8f ;Bank1 Source:18f
_ADDRESS_BUFh EQU 0x90 ;Bank1 Source:190
_ADDRESS_BUFf EQU 0x91 ;Bank1 Source:191
_CTR_BUF EQU 0x92 ;Bank1 Source:192
_Reg_Adr EQU 0x93 ;Bank1 Source:193
_HEP1_CNT EQU 0x94 ;Bank1 Source:194
_STACK_IAP0 EQU 0x95 ;Bank1 Source:195
_bmRequestType EQU 0xc0 ;Bank1 Source:1c0
_bRequest EQU 0xc1 ;Bank1 Source:1c1
_wValueL EQU 0xc2 ;Bank1 Source:1c2
_wValueH EQU 0xc3 ;Bank1 Source:1c3
_wIndexL EQU 0xc4 ;Bank1 Source:1c4
_wIndexH EQU 0xc5 ;Bank1 Source:1c5
_wLengthL EQU 0xc6 ;Bank1 Source:1c6
_wLengthH EQU 0xc7 ;Bank1 Source:1c7
_TBLL EQU 0xc8 ;Bank1 Source:1c8
_ROMADRL EQU 0xc9 ;Bank1 Source:1c9
_ROMADRH EQU 0xca ;Bank1 Source:1ca
_STATUS_BUF EQU 0xcb ;Bank1 Source:1cb
_USBTR EQU 0xcc ;Bank1 Source:1cc
_GCNTR EQU 0xcd ;Bank1 Source:1cd
_EP1CNTR EQU 0xce ;Bank1 Source:1ce
_EP2CNTR EQU 0xcf ;Bank1 Source:1cf
_EP3CNTR EQU 0xd0 ;Bank1 Source:1d0
_EPINTR EQU 0xd1 ;Bank1 Source:1d1
_EPINTE EQU 0xd2 ;Bank1 Source:1d2
_STAINTR EQU 0xd3 ;Bank1 Source:1d3
_STAINTE EQU 0xd4 ;Bank1 Source:1d4
_FAR EQU 0xd5 ;Bank1 Source:1d5
_EP0RXTR EQU 0xd6 ;Bank1 Source:1d6
_EP0RXCSR EQU 0xd7 ;Bank1 Source:1d7
_EP0TXCSR EQU 0xd8 ;Bank1 Source:1d8
_EP1CSR EQU 0xd9 ;Bank1 Source:1d9
_EP2CSR EQU 0xda ;Bank1 Source:1da
_EP3CSR EQU 0xdb ;Bank1 Source:1db
_EP0RXCTR EQU 0xdc ;Bank1 Source:1dc
_EP0TXCTR EQU 0xdd ;Bank1 Source:1dd
_EP1CTR EQU 0xde ;Bank1 Source:1de
_EP2CTR EQU 0xdf ;Bank1 Source:1df
_EP3CTR EQU 0xe0 ;Bank1 Source:1e0
_EP0RXDAR EQU 0xe1 ;Bank1 Source:1e1
_EP0TXDAR EQU 0xe2 ;Bank1 Source:1e2
_EP1DAR EQU 0xe3 ;Bank1 Source:1e3
_EP2DAR EQU 0xe4 ;Bank1 Source:1e4
_EP3DAR EQU 0xe5 ;Bank1 Source:1e5
_HGSR EQU 0xe6 ;Bank1 Source:1e6
_HINTR EQU 0xe7 ;Bank1 Source:1e7
_HINTE EQU 0xe8 ;Bank1 Source:1e8
_HAR EQU 0xe9 ;Bank1 Source:1e9
_HEP0RXTR EQU 0xea ;Bank1 Source:1ea
_HEP0RXCSR EQU 0xeb ;Bank1 Source:1eb
_HEP0TXCSR EQU 0xec ;Bank1 Source:1ec
_HEP1TXCSR EQU 0xed ;Bank1 Source:1ed
_HEP0RXCTR EQU 0xee ;Bank1 Source:1ee
_HEP0TXCTR EQU 0xef ;Bank1 Source:1ef
_HEP0RXDAR EQU 0xf0 ;Bank1 Source:1f0
_HEP0TXDAR EQU 0xf1 ;Bank1 Source:1f1
_HEP1TXDAR EQU 0xf2 ;Bank1 Source:1f2
_HPCONR EQU 0xf3 ;Bank1 Source:1f3
_HPSTAR EQU 0xf4 ;Bank1 Source:1f4
_HSR EQU 0xf5 ;Bank1 Source:1f5
_HPSR1 EQU 0xf6 ;Bank1 Source:1f6
_HPSR2 EQU 0xf7 ;Bank1 Source:1f7
_HPSR3 EQU 0xf8 ;Bank1 Source:1f8
_HPSR4 EQU 0xf9 ;Bank1 Source:1f9
_HPSCR1 EQU 0xfa ;Bank1 Source:1fa
_HPSCR2 EQU 0xfb ;Bank1 Source:1fb
_HPSCR3 EQU 0xfc ;Bank1 Source:1fc
_HPSCR4 EQU 0xfd ;Bank1 Source:1fd
_FNLR EQU 0xfe ;Bank1 Source:1fe
_FNHR EQU 0xff ;Bank1 Source:1ff
_USBBulkState EQU 0x31
_ET21x130_RAWDATA EQU 0x15
_ET12x130_TestPin EQU 0x16
_ET21x130_CTRL EQU 0x17
;--------------------------------------------------------
;--------------------------------------------------------
; internal ram data
; .area DSEG (DATA)
; _psz
; _psz_1
_nHwLength EQU 0x86 ;Bank1 Source:186
_nwLength EQU 0xc6 ;Bank1 Source:1c6
_nRomAdr EQU 0xc9 ;Bank1 Source:1c9
_nTable EQU 0x0b
_nAddrBuf EQU 0x90 ;Bank1 Source:190
_usb_byTemp EQU 0x92 ;Bank1 Source:192
_RAW_Address EQU 0x32
_RAW_Bank EQU 0x33
_FIFO_Stock EQU 0x34
_USB_FIFO_Bank EQU 0x35
_STOCK_Counter EQU 0x36
_RowPixelCounter EQU 0x37
_YDummyCounter EQU 0x38
_ColLineCount EQU 0x3a
_TEMP_count EQU 0x3b
_TestData EQU 0x3c
_BackUp_RAMBS1 EQU 0x3d
_BackUp_IAP1 EQU 0x3e
_Sensor_Flag EQU 0x3f
_HostCommand0 EQU 0x40
_HostCommand1 EQU 0x41
_HostCommand2 EQU 0x42
_HostCommand3 EQU 0x43
_HostCommand4 EQU 0x44
_I2CRegR0 EQU 0x45
_I2CRegR0_H EQU 0x45
_I2CRegR0_L EQU 0x46
_I2CRegR1 EQU 0x47
_I2CRegR1_H EQU 0x47
_I2CRegR1_L EQU 0x48
_I2CRegR2 EQU 0x49
_I2CRegR2_H EQU 0x49
_I2CRegR2_L EQU 0x4a
_I2CRegR3 EQU 0x4b
_I2CRegR3_H EQU 0x4b
_I2CRegR3_L EQU 0x4c
_I2CRegR4 EQU 0x4d
_I2CRegR4_H EQU 0x4d
_I2CRegR4_L EQU 0x4e
_I2CRegR5 EQU 0x4f
_I2CRegR5_H EQU 0x4f
_I2CRegR5_L EQU 0x50
_I2CRegR6 EQU 0x51
_I2CRegR6_H EQU 0x51
_I2CRegR6_L EQU 0x52
_I2CRegR7 EQU 0x53
_I2CRegR7_H EQU 0x53
_I2CRegR7_L EQU 0x54
_I2CRegR8 EQU 0x55
_I2CRegR8_H EQU 0x55
_I2CRegR8_L EQU 0x56
_I2C_Reg_Index EQU 0x5e
_I2C_Reg_Index_L EQU 0x5f
_I2C_Reg_Index_H EQU 0x5e
_COUNTER_16 EQU 0x5d
_I2C_RxTx_Data EQU 0x5b
_I2C_RxTx_Data_L EQU 0x5c
_I2C_RxTx_Data_H EQU 0x5b
;--------------------------------------------------------
; Bit registers
; Allocated Registers
; Direct Registers
; Stack Register
s0xF0 EQU 0xf0 ;bank0
s0xF1 EQU 0xf1 ;bank0
s0xF2 EQU 0xf2 ;bank0
;--------------------------------------------------------
; overlayable items in internal ram
;--------------------------------------------------------
; .area OSEG (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
; .area ISEG (DATA)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
; .area XSEG (XDATA)
;--------------------------------------------------------
; interrupt vector
;--------------------------------------------------------
; .area CSEG (CODE)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
; .area GSINIT (CODE)
; .area GSFINAL (CODE)
; .area GSINIT (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
; .area CSEG (CODE)
;***
; pBlock Stats: dbName = C
;***
;entry: _I2C_Read_SartBit: ;Function start
; 1 exit point
;Using Bank: Bank0
;has an exit
;; Starting pCode block
_I2C_Read_SartBit: ;Function start
; 1 exit point
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (295)
; M_BC(I2C_PORT, SData); //_SData=0
BC _ET21x130_CTRL,2
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (300)
; M_BC(I2C_PORT, SCLK); //SCLK=0 -> START,此時I2C總線啟動
BC _ET21x130_CTRL,3
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (306)
; M_BC(I2C_PORT, SData); //SData=0 -> Read(讀寫位0-->read;1-->write)
BC _ET21x130_CTRL,2
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (307)
; M_BS(I2C_PORT, SCLK); //SCLK=1
BS _ET21x130_CTRL,3
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
NOP ;inline asm
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (312)
; M_BC(I2C_PORT, SCLK); //SCLK=0
BC _ET21x130_CTRL,3
RET
; exit point of _I2C_Read_SartBit
;***
; pBlock Stats: dbName = C
;***
;entry: _I2C_Write_SartBit: ;Function start
; 1 exit point
;Using Bank: Bank0
;has an exit
;; Starting pCode block
_I2C_Write_SartBit: ;Function start
; 1 exit point
;#CSRC F:\左開中\ETOM\ET21X130D攝像頭演示\C\ET21x130_I2C.c (272)
; M_BC(I2C_PORT, SData); //_SData=0
BC _ET21x130_CTRL,2
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