library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
entity led1 is
port(ledin:in std_logic_vector(3 downto 0);
ledout:out std_logic_vector(6 downto 0));
end led1;

architecture a_led of led1 is
begin
process(ledin)
begin 
case ledin is --The sequence is "g f e d c b a"
when "0000" => ledout<="0111111"; -- " show 0 "
when "0001" => ledout<="0000110"; -- " show 1 "
when "0010" => ledout<="1011011"; -- " show 2 "
when "0011" => ledout<="1001111"; -- " show 3 "
when "0100" => ledout<="1100110"; -- " show 4 "
when "0101" => ledout<="1101101"; -- " show 5 "
when "0110" => ledout<="1111101"; -- " show 6 "
when "0111" => ledout<="0000111"; -- " show 7 "
when "1000" => ledout<="1111111"; -- " show 8 "
when "1001" => ledout<="1101111"; -- " show 9 "
when "1010" => ledout<="1110111"; -- " show 10 "
when "1011" => ledout<="1111100"; -- " show 11 "
when "1100" => ledout<="0111001"; -- " show 12 "
when "1101" => ledout<="1011110"; -- " show 13 " 
when "1110" => ledout<="1111001"; -- " show 14 "
when "1111" => ledout<="1110001"; -- " show 15 "
when others => ledout<="XXXXXXX"; --必須有,Here it is 'X',single quote
end case;
end process ;
end a_led;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity lift1 is
port (
clk: in STD_LOGIC; --2hz信號
upin: in STD_LOGIC; --上升請求鍵
downin: in STD_LOGIC; --下降請求鍵
st_ch: in STD_LOGIC; --樓層選擇鍵
close: in STD_LOGIC; --提前關(guān)門鍵
delay: in STD_LOGIC; --延時關(guān)門鍵
run_stop: in STD_LOGIC; --電梯運行開關(guān)
lamp: out STD_LOGIC; --運行或停止燈
run_waitdis: out STD_LOGIC_VECTOR (6 downto 0); --運行或等待時間
st_outdis: out STD_LOGIC_VECTOR (6 downto 0); --電梯所在樓層指示
directdis: out STD_LOGIC_VECTOR (6 downto 0) --樓層選擇指示
);
end lift1;

architecture lift1_arch of lift1 is
component led1
port(ledin:in std_logic_vector(3 downto 0);
ledout:out std_logic_vector(6 downto 0));
end component;

signal ur,dr:STD_LOGIC_VECTOR (6 downto 1);
signal dir,liftor:integer range 0 to 5;
signal wai_t:STD_LOGIC_VECTOR (2 downto 0);
signal divide,hand,clkin:STD_LOGIC;
signal ladd:STD_LOGIC_VECTOR (1 downto 0);
signal closex,delayx:STD_LOGIC;
signal run_wait: STD_LOGIC_VECTOR (3 downto 0);
signal st_out: STD_LOGIC_VECTOR (3 downto 0);
signal direct: STD_LOGIC_VECTOR (3 downto 0);

begin
direct<='0'&conv_std_logic_vector(dir,3)+1;
st_out<='0'&conv_std_logic_vector(liftor,3)+1;
run_wait<='0'&wai_t;
lamp<=ladd(1);
hand<=wai_t(2) and (not wai_t(1)) and wai_t(0);
closex<=close and (not ladd(1));
delayx<=delay and (not ladd(1));

urun_wait:led1 port map(run_wait,run_waitdis);
ust_out:led1 port map(st_out,st_outdis);
udirect:led1 port map(direct,directdis);

p0:process(clk)
begin
if (clk'event and clk='1') then
clkin<=not clkin;
end if;
end process p0;

p1:process(clkin)
begin
if (clkin'event and clkin='1') then
divide<=not divide;
if (dir=5) then
dir<=0;
else
dir<=dir+1;
end if;
end if;
end process p1;

p2:process(ur,dr,dir,upin,downin,st_ch,liftor,wai_t,run_stop,hand)
variable num,t:integer range 0 to 6;
begin
num:=liftor+1;
t:=dir+1;
if (run_stop='1') then
if (((t>num) and (st_ch='1')) or (upin='1')) then
case t is
when 1 => ur(1)<='1';
when 2 => ur(2)<='1';
when 3 => ur(3)<='1';
when 4 => ur(4)<='1';
when 5 => ur(5)<='1';
when 6 => ur(6)<='1';
when others =>Null;
end case;
elsif (hand='1') then 
case num is
when 1 => ur(1)<='0';
when 2 => ur(2)<='0';
when 3 => ur(3)<='0';
when 4 => ur(4)<='0';
when 5 => ur(5)<='0';
when 6 => ur(6)<='0';
when others =>Null;
end case;
end if;
if (((t<num) and (st_ch='1')) or (downin='1')) then
case t is
when 1 => dr(1)<='1';
when 2 => dr(2)<='1';
when 3 => dr(3)<='1';
when 4 => dr(4)<='1';
when 5 => dr(5)<='1';
when 6 => dr(6)<='1';
when others =>Null;
end case;
elsif (hand='1') then
case num is
when 1 => dr(1)<='0';
when 2 => dr(2)<='0';
when 3 => dr(3)<='0';
when 4 => dr(4)<='0';
when 5 => dr(5)<='0';
when 6 => dr(6)<='0';
when others =>Null;
end case;
end if;
else
ur<="000000";
dr<="000000";
end if;
end process p2;

p3:process(ur,dr,liftor,ladd,wai_t,run_stop)
begin
if (run_stop='1') then
if (wai_t="110") then
if ((ur or dr)="000000") then
ladd(1)<='0';
else
case liftor is
when 0 =>if ((ur(1) or dr(1))>'0') then
ladd(1)<='0';
else
ladd<="11";
end if;
when 1 =>if ((ur(2) or dr(2))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 3) or dr(6 downto 3))>"0000")) or((ur(1) or dr(1))='0')) then
ladd<="11";
else
ladd<="10";
end if; 
when 2 =>if ((ur(3) or dr(3))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 4) or dr(6 downto 4))>"000")) or((ur(2 downto 1) or dr(2 downto 1))="00")) then
ladd<="11";
else
ladd<="10";
end if; 
when 3 =>if ((ur(4) or dr(4))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 5) or dr(6 downto 5))>"00")) or((ur(3 downto 1) or dr(3 downto 1))="000")) then
ladd<="11";
else
ladd<="10";
end if;
when 4 =>if ((ur(5) or dr(5))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6) or dr(6))>'0')) or((ur(4 downto 1) or dr(4 downto 1))="0000")) then
ladd<="11";
else
ladd<="10";
end if;
when 5 =>if ((ur(6) or dr(6))>'0') then
ladd(1)<='0'; 
else
ladd<="10";
end if;
when others=>null;
end case;
end if;
end if;
else
ladd<="00";
end if;
end process p3;

p4:process(divide,wai_t,ladd,closex,delayx)
begin
if (divide'event and divide='1') then
if (wai_t="000" or closex='1') then
wai_t<="110";
else
if (delayx='0') then
wai_t<=wai_t-1;
else
wai_t<="010";
end if;
if (wai_t="001") then
if (ladd="11") then 
liftor<=liftor+1;
elsif (ladd="10") then
liftor<=liftor-1;
end if;
end if;
end if;
end if;
end process p4;
end lift1_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity lifter is
port (
clk: in STD_LOGIC; --4mhz信號
upin: in STD_LOGIC; --上升請求鍵
downin: in STD_LOGIC; --下降請求鍵
st_ch: in STD_LOGIC; --樓層選擇鍵
close: in STD_LOGIC; --提前關(guān)門鍵
delay: in STD_LOGIC; --延時關(guān)門鍵
run_stop: in STD_LOGIC; --電梯運行開關(guān)
lamp: out STD_LOGIC; --運行或停止燈
selout:out STD_LOGIC_VECTOR (2 downto 0);
segout: out STD_LOGIC_VECTOR (6 downto 0) 
);
end lifter;

architecture lift1_arch of lifter is
component led1
port(ledin:in std_logic_vector(3 downto 0);
ledout:out std_logic_vector(6 downto 0));
end component;

signal ur,dr:STD_LOGIC_VECTOR (6 downto 1);
signal dir,liftor:integer range 0 to 5;
signal wai_t:STD_LOGIC_VECTOR (2 downto 0);
signal div,cp,hand,clkin:STD_LOGIC;
signal ladd,s:STD_LOGIC_VECTOR (1 downto 0);
signal closex,delayx:STD_LOGIC;
signal run_wait: STD_LOGIC_VECTOR (3 downto 0);
signal st_out: STD_LOGIC_VECTOR (3 downto 0);
signal direct: STD_LOGIC_VECTOR (3 downto 0);
signal dout: STD_LOGIC_VECTOR (3 downto 0);
signal q:STD_LOGIC_VECTOR (21 downto 0);

begin
direct<='0'&conv_std_logic_vector(dir,3)+1;
st_out<='0'&conv_std_logic_vector(liftor,3)+1;
run_wait<='0'&wai_t;
lamp<=ladd(1);
hand<=wai_t(2) and (not wai_t(1)) and wai_t(0);
closex<=(not close) and (not ladd(1));
delayx<=(not delay) and (not ladd(1));
selout<="001" when s=0 else
"010" when s=1 else
"100" when s=2 else
"000";
dout<=direct when s=0 else
run_wait when s=1 else
st_out when s=2 else
"0000000";

u:led1 port map(dout,segout);

p0:process(clk)
begin
if (clk'event and clk='1') then
q<=q+1;
end if;
end process p0;
cp<=q(20);
s<=q(14 downto 13);
p1:process(cp)
begin
if (cp'event and cp='1') then
div<=not div;
if (dir=5) then
dir<=0;
else
dir<=dir+1;
end if;
end if;
end process p1;

p2:process(ur,dr,dir,upin,downin,st_ch,liftor,wai_t,run_stop,hand)
variable num,t:integer range 0 to 6;
begin
num:=liftor+1;
t:=dir+1;
if (run_stop='1') then
if (((t>num) and (st_ch='0')) or (upin='0')) then
case t is
when 1 => ur(1)<='1';
when 2 => ur(2)<='1';
when 3 => ur(3)<='1';
when 4 => ur(4)<='1';
when 5 => ur(5)<='1';
when 6 => ur(6)<='1';
when others =>Null;
end case;
elsif (hand='1') then 
case num is
when 1 => ur(1)<='0';
when 2 => ur(2)<='0';
when 3 => ur(3)<='0';
when 4 => ur(4)<='0';
when 5 => ur(5)<='0';
when 6 => ur(6)<='0';
when others =>Null;
end case;
end if;
if (((t<num) and (st_ch='0')) or (downin='0')) then
case t is
when 1 => dr(1)<='1';
when 2 => dr(2)<='1';
when 3 => dr(3)<='1';
when 4 => dr(4)<='1';
when 5 => dr(5)<='1';
when 6 => dr(6)<='1';
when others =>Null;
end case;
elsif (hand='1') then
case num is
when 1 => dr(1)<='0';
when 2 => dr(2)<='0';
when 3 => dr(3)<='0';
when 4 => dr(4)<='0';
when 5 => dr(5)<='0';
when 6 => dr(6)<='0';
when others =>Null;
end case;
end if;
else
ur<="000000";
dr<="000000";
end if;
end process p2;

p3:process(ur,dr,liftor,ladd,wai_t,run_stop)
begin
if (run_stop='1') then
if (wai_t="110") then
if ((ur or dr)="000000") then
ladd(1)<='0';
else
case liftor is
when 0 =>if ((ur(1) or dr(1))>'0') then
ladd(1)<='0';
else
ladd<="11";
end if;
when 1 =>if ((ur(2) or dr(2))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 3) or dr(6 downto 3))>"0000")) or((ur(1) or dr(1))='0')) then
ladd<="11";
else
ladd<="10";
end if; 
when 2 =>if ((ur(3) or dr(3))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 4) or dr(6 downto 4))>"000")) or((ur(2 downto 1) or dr(2 downto 1))="00")) then
ladd<="11";
else
ladd<="10";
end if; 
when 3 =>if ((ur(4) or dr(4))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6 downto 5) or dr(6 downto 5))>"00")) or((ur(3 downto 1) or dr(3 downto 1))="000")) then
ladd<="11";
else
ladd<="10";
end if;
when 4 =>if ((ur(5) or dr(5))>'0') then
ladd(1)<='0';
elsif(((ladd(0)='1') and ((ur(6) or dr(6))>'0')) or((ur(4 downto 1) or dr(4 downto 1))="0000")) then
ladd<="11";
else
ladd<="10";
end if;
when 5 =>if ((ur(6) or dr(6))>'0') then
ladd(1)<='0'; 
else
ladd<="10";
end if;
when others=>null;
end case;
end if;
end if;
else
ladd<="00";
end if;
end process p3;

p4:process(div,wai_t,ladd,closex,delayx)
begin
if (div'event and div='1') then
if (wai_t="000" or closex='1') then
wai_t<="110";
else
if (delayx='0') then
wai_t<=wai_t-1;
else
wai_t<="010";
end if;
if (wai_t="001") then
if (ladd="11") then 
liftor<=liftor+1;
elsif (ladd="10") then
liftor<=liftor-1;
end if;
end if;
end if;
end if;
end process p4;
end lift1_arch;