/* $Id: icc.c,v 1.8.2.3 2004/01/13 14:31:25 keil Exp $ * * ICC specific routines * * Author       Matt Henderson & Guy Ellis * Copyright    by Traverse Technologies Pty Ltd, www.travers.com.au *  * This software may be used and distributed according to the terms * of the GNU General Public License, incorporated herein by reference. * * 1999.6.25 Initial implementation of routines for Siemens ISDN * Communication Controller PEB 2070 based on the ISAC routines * written by Karsten Keil. * */#include <linux/init.h>#include "hisax.h"#include "icc.h"// #include "arcofi.h"#include "isdnl1.h"#include <linux/interrupt.h>#define DBUSY_TIMER_VALUE 80#define ARCOFI_USE 0static char *ICCVer[] __initdata ={"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};voidICCVersion(struct IsdnCardState *cs, char *s){	int val;	val = cs->readisac(cs, ICC_RBCH);	printk(KERN_INFO "%s ICC version (%x): %s\n", s, val, ICCVer[(val >> 5) & 3]);}static voidph_command(struct IsdnCardState *cs, unsigned int command){	if (cs->debug & L1_DEB_ISAC)		debugl1(cs, "ph_command %x", command);	cs->writeisac(cs, ICC_CIX0, (command << 2) | 3);}static voidicc_new_ph(struct IsdnCardState *cs){	switch (cs->dc.icc.ph_state) {		case (ICC_IND_EI1):			ph_command(cs, ICC_CMD_DI);			l1_msg(cs, HW_RESET | INDICATION, NULL);			break;		case (ICC_IND_DC):			l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);			break;		case (ICC_IND_DR):			l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);			break;		case (ICC_IND_PU):			l1_msg(cs, HW_POWERUP | CONFIRM, NULL);			break;		case (ICC_IND_FJ):			l1_msg(cs, HW_RSYNC | INDICATION, NULL);			break;		case (ICC_IND_AR):			l1_msg(cs, HW_INFO2 | INDICATION, NULL);			break;		case (ICC_IND_AI):			l1_msg(cs, HW_INFO4 | INDICATION, NULL);			break;		default:			break;	}}static voidicc_bh(struct IsdnCardState *cs){	struct PStack *stptr;		if (!cs)		return;	if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {		if (cs->debug)			debugl1(cs, "D-Channel Busy cleared");		stptr = cs->stlist;		while (stptr != NULL) {			stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);			stptr = stptr->next;		}	}	if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))		icc_new_ph(cs);			if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))		DChannel_proc_rcv(cs);	if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))		DChannel_proc_xmt(cs);#if ARCOFI_USE	if (!test_bit(HW_ARCOFI, &cs->HW_Flags))		return;	if (test_and_clear_bit(D_RX_MON1, &cs->event))		arcofi_fsm(cs, ARCOFI_RX_END, NULL);	if (test_and_clear_bit(D_TX_MON1, &cs->event))		arcofi_fsm(cs, ARCOFI_TX_END, NULL);#endif}voidicc_empty_fifo(struct IsdnCardState *cs, int count){	u_char *ptr;	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))		debugl1(cs, "icc_empty_fifo");	if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {		if (cs->debug & L1_DEB_WARN)			debugl1(cs, "icc_empty_fifo overrun %d",				cs->rcvidx + count);		cs->writeisac(cs, ICC_CMDR, 0x80);		cs->rcvidx = 0;		return;	}	ptr = cs->rcvbuf + cs->rcvidx;	cs->rcvidx += count;	cs->readisacfifo(cs, ptr, count);	cs->writeisac(cs, ICC_CMDR, 0x80);	if (cs->debug & L1_DEB_ISAC_FIFO) {		char *t = cs->dlog;		t += sprintf(t, "icc_empty_fifo cnt %d", count);		QuickHex(t, ptr, count);		debugl1(cs, cs->dlog);	}}static voidicc_fill_fifo(struct IsdnCardState *cs){	int count, more;	u_char *ptr;	if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))		debugl1(cs, "icc_fill_fifo");	if (!cs->tx_skb)		return;	count = cs->tx_skb->len;	if (count <= 0)		return;	more = 0;	if (count > 32) {		more = !0;		count = 32;	}	ptr = cs->tx_skb->data;	skb_pull(cs->tx_skb, count);	cs->tx_cnt += count;	cs->writeisacfifo(cs, ptr, count);	cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa);	if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {		debugl1(cs, "icc_fill_fifo dbusytimer running");		del_timer(&cs->dbusytimer);	}	init_timer(&cs->dbusytimer);	cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);	add_timer(&cs->dbusytimer);	if (cs->debug & L1_DEB_ISAC_FIFO) {		char *t = cs->dlog;		t += sprintf(t, "icc_fill_fifo cnt %d", count);		QuickHex(t, ptr, count);		debugl1(cs, cs->dlog);	}}voidicc_interrupt(struct IsdnCardState *cs, u_char val){	u_char exval, v1;	struct sk_buff *skb;	unsigned int count;	if (cs->debug & L1_DEB_ISAC)		debugl1(cs, "ICC interrupt %x", val);	if (val & 0x80) {	/* RME */		exval = cs->readisac(cs, ICC_RSTA);		if ((exval & 0x70) != 0x20) {			if (exval & 0x40) {				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "ICC RDO");#ifdef ERROR_STATISTIC				cs->err_rx++;#endif			}			if (!(exval & 0x20)) {				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "ICC CRC error");#ifdef ERROR_STATISTIC				cs->err_crc++;#endif			}			cs->writeisac(cs, ICC_CMDR, 0x80);		} else {			count = cs->readisac(cs, ICC_RBCL) & 0x1f;			if (count == 0)				count = 32;			icc_empty_fifo(cs, count);			if ((count = cs->rcvidx) > 0) {				cs->rcvidx = 0;				if (!(skb = alloc_skb(count, GFP_ATOMIC)))					printk(KERN_WARNING "HiSax: D receive out of memory\n");				else {					memcpy(skb_put(skb, count), cs->rcvbuf, count);					skb_queue_tail(&cs->rq, skb);				}			}		}		cs->rcvidx = 0;		schedule_event(cs, D_RCVBUFREADY);	}	if (val & 0x40) {	/* RPF */		icc_empty_fifo(cs, 32);	}	if (val & 0x20) {	/* RSC */		/* never */		if (cs->debug & L1_DEB_WARN)			debugl1(cs, "ICC RSC interrupt");	}	if (val & 0x10) {	/* XPR */		if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))			del_timer(&cs->dbusytimer);		if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))			schedule_event(cs, D_CLEARBUSY);		if (cs->tx_skb) {			if (cs->tx_skb->len) {				icc_fill_fifo(cs);				goto afterXPR;			} else {				dev_kfree_skb_irq(cs->tx_skb);				cs->tx_cnt = 0;				cs->tx_skb = NULL;			}		}		if ((cs->tx_skb = skb_dequeue(&cs->sq))) {			cs->tx_cnt = 0;			icc_fill_fifo(cs);		} else			schedule_event(cs, D_XMTBUFREADY);	}      afterXPR:	if (val & 0x04) {	/* CISQ */		exval = cs->readisac(cs, ICC_CIR0);		if (cs->debug & L1_DEB_ISAC)			debugl1(cs, "ICC CIR0 %02X", exval );		if (exval & 2) {			cs->dc.icc.ph_state = (exval >> 2) & 0xf;			if (cs->debug & L1_DEB_ISAC)				debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state);			schedule_event(cs, D_L1STATECHANGE);		}		if (exval & 1) {			exval = cs->readisac(cs, ICC_CIR1);			if (cs->debug & L1_DEB_ISAC)				debugl1(cs, "ICC CIR1 %02X", exval );		}	}	if (val & 0x02) {	/* SIN */		/* never */		if (cs->debug & L1_DEB_WARN)			debugl1(cs, "ICC SIN interrupt");	}	if (val & 0x01) {	/* EXI */		exval = cs->readisac(cs, ICC_EXIR);		if (cs->debug & L1_DEB_WARN)			debugl1(cs, "ICC EXIR %02x", exval);		if (exval & 0x80) {  /* XMR */			debugl1(cs, "ICC XMR");			printk(KERN_WARNING "HiSax: ICC XMR\n");		}		if (exval & 0x40) {  /* XDU */			debugl1(cs, "ICC XDU");			printk(KERN_WARNING "HiSax: ICC XDU\n");#ifdef ERROR_STATISTIC			cs->err_tx++;#endif			if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))				del_timer(&cs->dbusytimer);			if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))				schedule_event(cs, D_CLEARBUSY);			if (cs->tx_skb) { /* Restart frame */				skb_push(cs->tx_skb, cs->tx_cnt);				cs->tx_cnt = 0;				icc_fill_fifo(cs);			} else {				printk(KERN_WARNING "HiSax: ICC XDU no skb\n");				debugl1(cs, "ICC XDU no skb");			}		}		if (exval & 0x04) {  /* MOS */			v1 = cs->readisac(cs, ICC_MOSR);			if (cs->debug & L1_DEB_MONITOR)				debugl1(cs, "ICC MOSR %02x", v1);#if ARCOFI_USE			if (v1 & 0x08) {				if (!cs->dc.icc.mon_rx) {					if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {						if (cs->debug & L1_DEB_WARN)							debugl1(cs, "ICC MON RX out of memory!");						cs->dc.icc.mocr &= 0xf0;						cs->dc.icc.mocr |= 0x0a;						cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);						goto afterMONR0;					} else						cs->dc.icc.mon_rxp = 0;				}				if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {					cs->dc.icc.mocr &= 0xf0;					cs->dc.icc.mocr |= 0x0a;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					cs->dc.icc.mon_rxp = 0;					if (cs->debug & L1_DEB_WARN)						debugl1(cs, "ICC MON RX overflow!");					goto afterMONR0;				}				cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);				if (cs->debug & L1_DEB_MONITOR)					debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);				if (cs->dc.icc.mon_rxp == 1) {					cs->dc.icc.mocr |= 0x04;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				}			}		      afterMONR0:			if (v1 & 0x80) {				if (!cs->dc.icc.mon_rx) {					if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {						if (cs->debug & L1_DEB_WARN)