/*------------------------------------------------------------------------ . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. . . Copyright (C) 1996 by Erik Stahlman . Copyright (C) 2001 Standard Microsystems Corporation .	Developed by Simple Network Magic Corporation . Copyright (C) 2003 Monta Vista Software, Inc. .	Unified SMC91x driver by Nicolas Pitre . . This program is free software; you can redistribute it and/or modify . it under the terms of the GNU General Public License as published by . the Free Software Foundation; either version 2 of the License, or . (at your option) any later version. . . This program is distributed in the hope that it will be useful, . but WITHOUT ANY WARRANTY; without even the implied warranty of . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the . GNU General Public License for more details. . . You should have received a copy of the GNU General Public License . along with this program; if not, write to the Free Software . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA . . Information contained in this file was obtained from the LAN91C111 . manual from SMC.  To get a copy, if you really want one, you can find . information under www.smsc.com. . . Authors .	Erik Stahlman		<erik@vt.edu> .	Daris A Nevil		<dnevil@snmc.com> .	Nicolas Pitre 		<nico@cam.org> . ---------------------------------------------------------------------------*/#ifndef _SMC91X_H_#define _SMC91X_H_/* * Define your architecture specific bus configuration parameters here. */#if	defined(CONFIG_SA1100_GRAPHICSCLIENT) || \	defined(CONFIG_SA1100_PFS168) || \	defined(CONFIG_SA1100_FLEXANET) || \	defined(CONFIG_SA1100_GRAPHICSMASTER) || \	defined(CONFIG_ARCH_LUBBOCK)/* We can only do 16-bit reads and writes in the static memory space. */#define SMC_CAN_USE_8BIT	0#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	0#define SMC_NOWAIT		1/* The first two address lines aren't connected... */#define SMC_IO_SHIFT		2#define SMC_inw(a, r)		readw((a) + (r))#define SMC_outw(v, a, r)	writew(v, (a) + (r))#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)/* We can only do 16-bit reads and writes in the static memory space. */#define SMC_CAN_USE_8BIT	0#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	0#define SMC_NOWAIT		1#define SMC_IO_SHIFT		0#define SMC_inw(a, r)		in_be16((volatile u16 *)((a) + (r)))#define SMC_outw(v, a, r)	out_be16((volatile u16 *)((a) + (r)), v)#define SMC_insw(a, r, p, l) 						\	do {								\		unsigned long __port = (a) + (r);			\		u16 *__p = (u16 *)(p);					\		int __l = (l);						\		insw(__port, __p, __l);					\		while (__l > 0) {					\			*__p = swab16(*__p);				\			__p++;						\			__l--;						\		}							\	} while (0)#define SMC_outsw(a, r, p, l) 						\	do {								\		unsigned long __port = (a) + (r);			\		u16 *__p = (u16 *)(p);					\		int __l = (l);						\		while (__l > 0) {					\			/* Believe it or not, the swab isn't needed. */	\			outw( /* swab16 */ (*__p++), __port);		\			__l--;						\		}							\	} while (0)#define set_irq_type(irq, type)#elif defined(CONFIG_SA1100_ASSABET)#include <asm/arch/neponset.h>/* We can only do 8-bit reads and writes in the static memory space. */#define SMC_CAN_USE_8BIT	1#define SMC_CAN_USE_16BIT	0#define SMC_CAN_USE_32BIT	0#define SMC_NOWAIT		1/* The first two address lines aren't connected... */#define SMC_IO_SHIFT		2#define SMC_inb(a, r)		readb((a) + (r))#define SMC_outb(v, a, r)	writeb(v, (a) + (r))#define SMC_insb(a, r, p, l)	readsb((a) + (r), p, (l))#define SMC_outsb(a, r, p, l)	writesb((a) + (r), p, (l))#elif	defined(CONFIG_ARCH_INNOKOM) || \	defined(CONFIG_MACH_MAINSTONE) || \	defined(CONFIG_ARCH_PXA_IDP) || \	defined(CONFIG_ARCH_RAMSES)#define SMC_CAN_USE_8BIT	1#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	1#define SMC_IO_SHIFT		0#define SMC_NOWAIT		1#define SMC_USE_PXA_DMA		1#define SMC_inb(a, r)		readb((a) + (r))#define SMC_inw(a, r)		readw((a) + (r))#define SMC_inl(a, r)		readl((a) + (r))#define SMC_outb(v, a, r)	writeb(v, (a) + (r))#define SMC_outl(v, a, r)	writel(v, (a) + (r))#define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)#define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)/* We actually can't write halfwords properly if not word aligned */static inline voidSMC_outw(u16 val, unsigned long ioaddr, int reg){	if (reg & 2) {		unsigned int v = val << 16;		v |= readl(ioaddr + (reg & ~2)) & 0xffff;		writel(v, ioaddr + (reg & ~2));	} else {		writew(val, ioaddr + reg);	}}#elif	defined(CONFIG_ARCH_OMAP)#define INNOVATOR_1610_SMC_GPIO	0#define OSK_5912_SMC_GPIO	0#define H3_1710_SMC_GPIO	40/* We can only do 16-bit reads and writes in the static memory space. */#define SMC_CAN_USE_8BIT	0#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	0#define SMC_IO_SHIFT		0#define SMC_NOWAIT		1#define SMC_inb(a, r)		readb((a) + (r))#define SMC_outb(v, a, r)	writeb(v, (a) + (r))#define SMC_inw(a, r)		readw((a) + (r))#define SMC_outw(v, a, r)	writew(v, (a) + (r))#define SMC_insw(a, r, p, l)	readsw((a) + (r), p, l)#define SMC_outsw(a, r, p, l)	writesw((a) + (r), p, l)#define SMC_inl(a, r)		readl((a) + (r))#define SMC_outl(v, a, r)	writel(v, (a) + (r))#define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)#define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)#elif	defined(CONFIG_ISA)#define SMC_CAN_USE_8BIT	1#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	0#define SMC_inb(a, r)		inb((a) + (r))#define SMC_inw(a, r)		inw((a) + (r))#define SMC_outb(v, a, r)	outb(v, (a) + (r))#define SMC_outw(v, a, r)	outw(v, (a) + (r))#define SMC_insw(a, r, p, l)	insw((a) + (r), p, l)#define SMC_outsw(a, r, p, l)	outsw((a) + (r), p, l)#elif   defined(CONFIG_M32R)#define SMC_CAN_USE_8BIT	0#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	0#define SMC_inb(a, r)		inb((a) + (r) - 0xa0000000)#define SMC_inw(a, r)		inw((a) + (r) - 0xa0000000)#define SMC_outb(v, a, r)	outb(v, (a) + (r) - 0xa0000000)#define SMC_outw(v, a, r)	outw(v, (a) + (r) - 0xa0000000)#define SMC_insw(a, r, p, l)	insw((a) + (r) - 0xa0000000, p, l)#define SMC_outsw(a, r, p, l)	outsw((a) + (r) - 0xa0000000, p, l)#elif defined(CONFIG_ARCH_OMAP24XX)/* We can only do 16-bit reads and writes in the static memory sp */#define SMC_CAN_USE_8BIT       0#define SMC_CAN_USE_16BIT      1#define SMC_CAN_USE_32BIT      0#define SMC_IO_SHIFT           0#define SMC_NOWAIT             1#define SMC_inb(a, r)          readb((a) + (r))#define SMC_outb(v, a, r)      writeb(v, (a) + (r))#define SMC_inw(a, r)          readw((a) + (r))#define SMC_outw(v, a, r)      writew(v, (a) + (r))#define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)#define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)#define SMC_inl(a, r)          readl((a) + (r))#define SMC_outl(v, a, r)      writel(v, (a) + (r))#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)#else#define SMC_CAN_USE_8BIT	1#define SMC_CAN_USE_16BIT	1#define SMC_CAN_USE_32BIT	1#define SMC_NOWAIT		1#define SMC_inb(a, r)		readb((a) + (r))#define SMC_inw(a, r)		readw((a) + (r))#define SMC_inl(a, r)		readl((a) + (r))#define SMC_outb(v, a, r)	writeb(v, (a) + (r))#define SMC_outw(v, a, r)	writew(v, (a) + (r))#define SMC_outl(v, a, r)	writel(v, (a) + (r))#define SMC_insl(a, r, p, l)	readsl((a) + (r), p, l)#define SMC_outsl(a, r, p, l)	writesl((a) + (r), p, l)#define RPC_LSA_DEFAULT		RPC_LED_100_10#define RPC_LSB_DEFAULT		RPC_LED_TX_RX#endif#ifdef SMC_USE_PXA_DMA/* * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is * always happening in irq context so no need to worry about races.  TX is * different and probably not worth it for that reason, and not as critical * as RX which can overrun memory and lose packets. */#include <linux/pci.h>#include <asm/dma.h>#ifdef SMC_insl#undef SMC_insl#define SMC_insl(a, r, p, l) \	smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)static inline voidsmc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,		 u_char *buf, int len){	dma_addr_t dmabuf;	/* fallback if no DMA available */	if (dma == (unsigned char)-1) {		readsl(ioaddr + reg, buf, len);		return;	}	/* 64 bit alignment is required for memory to memory DMA */	if ((long)buf & 4) {		*((u32 *)buf)++ = SMC_inl(ioaddr, reg);		len--;	}	len *= 4;	dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);	DCSR(dma) = DCSR_NODESC;	DTADR(dma) = dmabuf;	DSADR(dma) = physaddr + reg;	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |		     DCMD_WIDTH4 | (DCMD_LENGTH & len));	DCSR(dma) = DCSR_NODESC | DCSR_RUN;	while (!(DCSR(dma) & DCSR_STOPSTATE));	DCSR(dma) = 0;	dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);}#endif#ifdef SMC_insw#undef SMC_insw#define SMC_insw(a, r, p, l) \	smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)static inline voidsmc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,		 u_char *buf, int len){	dma_addr_t dmabuf;	/* fallback if no DMA available */	if (dma == (unsigned char)-1) {		readsw(ioaddr + reg, buf, len);		return;	}	/* 64 bit alignment is required for memory to memory DMA */	while ((long)buf & 6) {		*((u16 *)buf)++ = SMC_inw(ioaddr, reg);		len--;	}	len *= 2;	dmabuf = dma_map_single(NULL, buf, len, PCI_DMA_FROMDEVICE);	DCSR(dma) = DCSR_NODESC;	DTADR(dma) = dmabuf;	DSADR(dma) = physaddr + reg;	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |		     DCMD_WIDTH2 | (DCMD_LENGTH & len));	DCSR(dma) = DCSR_NODESC | DCSR_RUN;	while (!(DCSR(dma) & DCSR_STOPSTATE));	DCSR(dma) = 0;	dma_unmap_single(NULL, dmabuf, len, PCI_DMA_FROMDEVICE);}#endifstatic voidsmc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs){	DCSR(dma) = 0;}#endif  /* SMC_USE_PXA_DMA *//* Because of bank switching, the LAN91x uses only 16 I/O ports */#ifndef SMC_IO_SHIFT#define SMC_IO_SHIFT	0#endif#define SMC_IO_EXTENT	(16 << SMC_IO_SHIFT)/* . Bank Select Register: . .		yyyy yyyy 0000 00xx .		xx 		= bank number .		yyyy yyyy	= 0x33, for identification purposes.*/#define BANK_SELECT		(14 << SMC_IO_SHIFT)// Transmit Control Register/* BANK 0  */#define TCR_REG 	SMC_REG(0x0000, 0)#define TCR_ENABLE	0x0001	// When 1 we can transmit#define TCR_LOOP	0x0002	// Controls output pin LBK#define TCR_FORCOL	0x0004	// When 1 will force a collision#define TCR_PAD_EN	0x0080	// When 1 will pad tx frames < 64 bytes w/0#define TCR_NOCRC	0x0100	// When 1 will not append CRC to tx frames#define TCR_MON_CSN	0x0400	// When 1 tx monitors carrier#define TCR_FDUPLX    	0x0800  // When 1 enables full duplex operation#define TCR_STP_SQET	0x1000	// When 1 stops tx if Signal Quality Error#define TCR_EPH_LOOP	0x2000	// When 1 enables EPH block loopback#define TCR_SWFDUP	0x8000	// When 1 enables Switched Full Duplex mode#define TCR_CLEAR	0	/* do NOTHING *//* the default settings for the TCR register : */#define TCR_DEFAULT	(TCR_ENABLE | TCR_PAD_EN)// EPH Status Register/* BANK 0  */#define EPH_STATUS_REG	SMC_REG(0x0002, 0)#define ES_TX_SUC	0x0001	// Last TX was successful#define ES_SNGL_COL	0x0002	// Single collision detected for last tx#define ES_MUL_COL	0x0004	// Multiple collisions detected for last tx#define ES_LTX_MULT	0x0008	// Last tx was a multicast#define ES_16COL	0x0010	// 16 Collisions Reached#define ES_SQET		0x0020	// Signal Quality Error Test#define ES_LTXBRD	0x0040	// Last tx was a broadcast#define ES_TXDEFR	0x0080	// Transmit Deferred#define ES_LATCOL	0x0200	// Late collision detected on last tx#define ES_LOSTCARR	0x0400	// Lost Carrier Sense#define ES_EXC_DEF	0x0800	// Excessive Deferral#define ES_CTR_ROL	0x1000	// Counter Roll Over indication#define ES_LINK_OK	0x4000	// Driven by inverted value of nLNK pin#define ES_TXUNRN	0x8000	// Tx Underrun// Receive Control Register/* BANK 0  */#define RCR_REG		SMC_REG(0x0004, 0)#define RCR_RX_ABORT	0x0001	// Set if a rx frame was aborted#define RCR_PRMS	0x0002	// Enable promiscuous mode#define RCR_ALMUL	0x0004	// When set accepts all multicast frames#define RCR_RXEN	0x0100	// IFF this is set, we can receive packets#define RCR_STRIP_CRC	0x0200	// When set strips CRC from rx packets#define RCR_ABORT_ENB	0x0200	// When set will abort rx on collision#define RCR_FILT_CAR	0x0400	// When set filters leading 12 bit s of carrier#define RCR_SOFTRST	0x8000 	// resets the chip/* the normal settings for the RCR register : */#define RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)#define RCR_CLEAR	0x0	// set it to a base state// Counter Register/* BANK 0  */#define COUNTER_REG	SMC_REG(0x0006, 0)// Memory Information Register/* BANK 0  */#define MIR_REG		SMC_REG(0x0008, 0)// Receive/Phy Control Register/* BANK 0  */#define RPC_REG		SMC_REG(0x000A, 0)#define RPC_SPEED	0x2000	// When 1 PHY is in 100Mbps mode.#define RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode#define RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode#define RPC_LSXA_SHFT	5	// Bits to shift LS2A,LS1A,LS0A to lsb#define RPC_LSXB_SHFT	2	// Bits to get LS2B,LS1B,LS0B to lsb#define RPC_LED_100_10	(0x00)	// LED = 100Mbps OR's with 10Mbps link detect#define RPC_LED_RES	(0x01)	// LED = Reserved#define RPC_LED_10	(0x02)	// LED = 10Mbps link detect#define RPC_LED_FD	(0x03)	// LED = Full Duplex Mode#define RPC_LED_TX_RX	(0x04)	// LED = TX or RX packet occurred#define RPC_LED_100	(0x05)	// LED = 100Mbps link dectect#define RPC_LED_TX	(0x06)	// LED = TX packet occurred#define RPC_LED_RX	(0x07)	// LED = RX packet occurred#ifndef RPC_LSA_DEFAULT#define RPC_LSA_DEFAULT	RPC_LED_100#endif#ifndef RPC_LSB_DEFAULT#define RPC_LSB_DEFAULT RPC_LED_FD#endif#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)/* Bank 0 0x0C is reserved */// Bank Select Register/* All Banks */#define BSR_REG		0x000E// Configuration Reg/* BANK 1 */#define CONFIG_REG	SMC_REG(0x0000,	1)#define CONFIG_EXT_PHY	0x0200	// 1=external MII, 0=internal Phy#define CONFIG_GPCNTRL	0x0400	// Inverse value drives pin nCNTRL#define CONFIG_NO_WAIT	0x1000	// When 1 no extra wait states on ISA bus#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low#define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)// Base Address Register/* BANK 1 */#define BASE_REG	SMC_REG(0x0002, 1)