/************************************************************************ * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com) * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice.  This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. ************************************************************************/#ifndef _S2IO_H#define _S2IO_H#define TBD 0#define BIT(loc)		(0x8000000000000000ULL >> (loc))#define vBIT(val, loc, sz)	(((u64)val) << (64-loc-sz))#ifndef BOOL#define BOOL    int#endif#ifndef TRUE#define TRUE    1#define FALSE   0#endif#undef SUCCESS#define SUCCESS 0#define FAILURE -1/* Maximum outstanding splits to be configured into xena. */typedef enum xena_max_outstanding_splits {	XENA_ONE_SPLIT_TRANSACTION = 0,	XENA_TWO_SPLIT_TRANSACTION = 1,	XENA_THREE_SPLIT_TRANSACTION = 2,	XENA_FOUR_SPLIT_TRANSACTION = 3,	XENA_EIGHT_SPLIT_TRANSACTION = 4,	XENA_TWELVE_SPLIT_TRANSACTION = 5,	XENA_SIXTEEN_SPLIT_TRANSACTION = 6,	XENA_THIRTYTWO_SPLIT_TRANSACTION = 7} xena_max_outstanding_splits;#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)/*  OS concerned variables and constants */#define WATCH_DOG_TIMEOUT   	5*HZ#define EFILL       			0x1234#define ALIGN_SIZE  			127#define	PCIX_COMMAND_REGISTER	0x62/* * Debug related variables. */#define DEBUG_ON TRUE/* different debug levels. */#define	ERR_DBG		0#define	INIT_DBG	1#define	INFO_DBG	2#define	TX_DBG		3#define	INTR_DBG	4/* Global variable that defines the present debug level of the driver. */int debug_level = ERR_DBG;	/* Default level. *//* DEBUG message print. */#define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)/* Protocol assist features of the NIC */#define L3_CKSUM_OK 0xFFFF#define L4_CKSUM_OK 0xFFFF#define S2IO_JUMBO_SIZE 9600/* The statistics block of Xena */typedef struct stat_block {#ifdef  __BIG_ENDIAN/* Tx MAC statistics counters. */	u32 tmac_frms;	u32 tmac_data_octets;	u64 tmac_drop_frms;	u32 tmac_mcst_frms;	u32 tmac_bcst_frms;	u64 tmac_pause_ctrl_frms;	u32 tmac_ttl_octets;	u32 tmac_ucst_frms;	u32 tmac_nucst_frms;	u32 tmac_any_err_frms;	u64 tmac_ttl_less_fb_octets;	u64 tmac_vld_ip_octets;	u32 tmac_vld_ip;	u32 tmac_drop_ip;	u32 tmac_icmp;	u32 tmac_rst_tcp;	u64 tmac_tcp;	u32 tmac_udp;	u32 reserved_0;/* Rx MAC Statistics counters. */	u32 rmac_vld_frms;	u32 rmac_data_octets;	u64 rmac_fcs_err_frms;	u64 rmac_drop_frms;	u32 rmac_vld_mcst_frms;	u32 rmac_vld_bcst_frms;	u32 rmac_in_rng_len_err_frms;	u32 rmac_out_rng_len_err_frms;	u64 rmac_long_frms;	u64 rmac_pause_ctrl_frms;	u64 rmac_unsup_ctrl_frms;	u32 rmac_ttl_octets;	u32 rmac_accepted_ucst_frms;	u32 rmac_accepted_nucst_frms;	u32 rmac_discarded_frms;	u32 rmac_drop_events;	u32 reserved_1;	u64 rmac_ttl_less_fb_octets;	u64 rmac_ttl_frms;	u64 reserved_2;	u32 reserved_3;	u32 rmac_usized_frms;	u32 rmac_osized_frms;	u32 rmac_frag_frms;	u32 rmac_jabber_frms;	u32 reserved_4;	u64 rmac_ttl_64_frms;	u64 rmac_ttl_65_127_frms;	u64 reserved_5;	u64 rmac_ttl_128_255_frms;	u64 rmac_ttl_256_511_frms;	u64 reserved_6;	u64 rmac_ttl_512_1023_frms;	u64 rmac_ttl_1024_1518_frms;	u32 reserved_7;	u32 rmac_ip;	u64 rmac_ip_octets;	u32 rmac_hdr_err_ip;	u32 rmac_drop_ip;	u32 rmac_icmp;	u32 reserved_8;	u64 rmac_tcp;	u32 rmac_udp;	u32 rmac_err_drp_udp;	u64 rmac_xgmii_err_sym;	u64 rmac_frms_q0;	u64 rmac_frms_q1;	u64 rmac_frms_q2;	u64 rmac_frms_q3;	u64 rmac_frms_q4;	u64 rmac_frms_q5;	u64 rmac_frms_q6;	u64 rmac_frms_q7;	u16 rmac_full_q0;	u16 rmac_full_q1;	u16 rmac_full_q2;	u16 rmac_full_q3;	u16 rmac_full_q4;	u16 rmac_full_q5;	u16 rmac_full_q6;	u16 rmac_full_q7;	u32 rmac_pause_cnt;	u32 reserved_9;	u64 rmac_xgmii_data_err_cnt;	u64 rmac_xgmii_ctrl_err_cnt;	u32 rmac_accepted_ip;	u32 rmac_err_tcp;/* PCI/PCI-X Read transaction statistics. */	u32 rd_req_cnt;	u32 new_rd_req_cnt;	u32 new_rd_req_rtry_cnt;	u32 rd_rtry_cnt;	u32 wr_rtry_rd_ack_cnt;/* PCI/PCI-X write transaction statistics. */	u32 wr_req_cnt;	u32 new_wr_req_cnt;	u32 new_wr_req_rtry_cnt;	u32 wr_rtry_cnt;	u32 wr_disc_cnt;	u32 rd_rtry_wr_ack_cnt;/*	DMA Transaction statistics. */	u32 txp_wr_cnt;	u32 txd_rd_cnt;	u32 txd_wr_cnt;	u32 rxd_rd_cnt;	u32 rxd_wr_cnt;	u32 txf_rd_cnt;	u32 rxf_wr_cnt;#else/* Tx MAC statistics counters. */	u32 tmac_data_octets;	u32 tmac_frms;	u64 tmac_drop_frms;	u32 tmac_bcst_frms;	u32 tmac_mcst_frms;	u64 tmac_pause_ctrl_frms;	u32 tmac_ucst_frms;	u32 tmac_ttl_octets;	u32 tmac_any_err_frms;	u32 tmac_nucst_frms;	u64 tmac_ttl_less_fb_octets;	u64 tmac_vld_ip_octets;	u32 tmac_drop_ip;	u32 tmac_vld_ip;	u32 tmac_rst_tcp;	u32 tmac_icmp;	u64 tmac_tcp;	u32 reserved_0;	u32 tmac_udp;/* Rx MAC Statistics counters. */	u32 rmac_data_octets;	u32 rmac_vld_frms;	u64 rmac_fcs_err_frms;	u64 rmac_drop_frms;	u32 rmac_vld_bcst_frms;	u32 rmac_vld_mcst_frms;	u32 rmac_out_rng_len_err_frms;	u32 rmac_in_rng_len_err_frms;	u64 rmac_long_frms;	u64 rmac_pause_ctrl_frms;	u64 rmac_unsup_ctrl_frms;	u32 rmac_accepted_ucst_frms;	u32 rmac_ttl_octets;	u32 rmac_discarded_frms;	u32 rmac_accepted_nucst_frms;	u32 reserved_1;	u32 rmac_drop_events;	u64 rmac_ttl_less_fb_octets;	u64 rmac_ttl_frms;	u64 reserved_2;	u32 rmac_usized_frms;	u32 reserved_3;	u32 rmac_frag_frms;	u32 rmac_osized_frms;	u32 reserved_4;	u32 rmac_jabber_frms;	u64 rmac_ttl_64_frms;	u64 rmac_ttl_65_127_frms;	u64 reserved_5;	u64 rmac_ttl_128_255_frms;	u64 rmac_ttl_256_511_frms;	u64 reserved_6;	u64 rmac_ttl_512_1023_frms;	u64 rmac_ttl_1024_1518_frms;	u32 rmac_ip;	u32 reserved_7;	u64 rmac_ip_octets;	u32 rmac_drop_ip;	u32 rmac_hdr_err_ip;	u32 reserved_8;	u32 rmac_icmp;	u64 rmac_tcp;	u32 rmac_err_drp_udp;	u32 rmac_udp;	u64 rmac_xgmii_err_sym;	u64 rmac_frms_q0;	u64 rmac_frms_q1;	u64 rmac_frms_q2;	u64 rmac_frms_q3;	u64 rmac_frms_q4;	u64 rmac_frms_q5;	u64 rmac_frms_q6;	u64 rmac_frms_q7;	u16 rmac_full_q3;	u16 rmac_full_q2;	u16 rmac_full_q1;	u16 rmac_full_q0;	u16 rmac_full_q7;	u16 rmac_full_q6;	u16 rmac_full_q5;	u16 rmac_full_q4;	u32 reserved_9;	u32 rmac_pause_cnt;	u64 rmac_xgmii_data_err_cnt;	u64 rmac_xgmii_ctrl_err_cnt;	u32 rmac_err_tcp;	u32 rmac_accepted_ip;/* PCI/PCI-X Read transaction statistics. */	u32 new_rd_req_cnt;	u32 rd_req_cnt;	u32 rd_rtry_cnt;	u32 new_rd_req_rtry_cnt;/* PCI/PCI-X Write/Read transaction statistics. */	u32 wr_req_cnt;	u32 wr_rtry_rd_ack_cnt;	u32 new_wr_req_rtry_cnt;	u32 new_wr_req_cnt;	u32 wr_disc_cnt;	u32 wr_rtry_cnt;/*	PCI/PCI-X Write / DMA Transaction statistics. */	u32 txp_wr_cnt;	u32 rd_rtry_wr_ack_cnt;	u32 txd_wr_cnt;	u32 txd_rd_cnt;	u32 rxd_wr_cnt;	u32 rxd_rd_cnt;	u32 rxf_wr_cnt;	u32 txf_rd_cnt;#endif} StatInfo_t;/* Structures representing different init time configuration * parameters of the NIC. *//* Maintains Per FIFO related information. */typedef struct tx_fifo_config {#define	MAX_AVAILABLE_TXDS	8192	u32 FifoLen;		/* specifies len of FIFO upto 8192, ie no of TxDLs *//* Priority definition */#define TX_FIFO_PRI_0               0	/*Highest */#define TX_FIFO_PRI_1               1#define TX_FIFO_PRI_2               2#define TX_FIFO_PRI_3               3#define TX_FIFO_PRI_4               4#define TX_FIFO_PRI_5               5#define TX_FIFO_PRI_6               6#define TX_FIFO_PRI_7               7	/*lowest */	u8 FifoPriority;	/* specifies pointer level for FIFO */	/* user should not set twos fifos with same pri */	u8 fNoSnoop;#define NO_SNOOP_TXD                0x01#define NO_SNOOP_TXD_BUFFER          0x02} tx_fifo_config_t;/* Maintains per Ring related information */typedef struct rx_ring_config {	u32 NumRxd;		/*No of RxDs per Rx Ring */#define RX_RING_PRI_0               0	/* highest */#define RX_RING_PRI_1               1#define RX_RING_PRI_2               2#define RX_RING_PRI_3               3#define RX_RING_PRI_4               4#define RX_RING_PRI_5               5#define RX_RING_PRI_6               6#define RX_RING_PRI_7               7	/* lowest */	u8 RingPriority;	/*Specifies service priority of ring */	/* OSM should not set any two rings with same priority */	u8 RingOrg;		/*Organization of ring */#define RING_ORG_BUFF1           0x01#define RX_RING_ORG_BUFF3           0x03#define RX_RING_ORG_BUFF5           0x05/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */#define BUFF_SZ_1                   22	/* ethernet header */#define BUFF_SZ_2                   (64+64)	/* max. IP+TCP header size */#define BUFF_SZ_3                   (1500-20-20)	/* TCP payload */#define BUFF_SZ_3_JUMBO             (9600-20-20)	/* Jumbo TCP payload */	u32 RxdThresh;		/*No of used Rxds NIC can store before transfer to host */#define DEFAULT_RXD_THRESHOLD       0x1	/* TODO */	u8 fNoSnoop;#define NO_SNOOP_RXD                0x01#define NO_SNOOP_RXD_BUFFER         0x02	u32 RxD_BackOff_Interval;#define RXD_BACKOFF_INTERVAL_DEF        0x0#define RXD_BACKOFF_INTERVAL_MIN        0x0#define RXD_BACKOFF_INTERVAL_MAX        0x0} rx_ring_config_t;/* This structure provides contains values of the tunable parameters  * of the H/W  */struct config_param {/* Tx Side */	u32 TxFIFONum;		/*Number of Tx FIFOs */#define MAX_TX_FIFOS 8	tx_fifo_config_t TxCfg[MAX_TX_FIFOS];	/*Per-Tx FIFO config */	u32 MaxTxDs;		/*Max no. of Tx buffer descriptor per TxDL */	BOOL TxVLANEnable;	/*TRUE: Insert VLAN ID, FALSE: Don't insert */#define TX_REQ_TIMEOUT_DEFAULT          0x0#define TX_REQ_TIMEOUT_MIN              0x0#define TX_REQ_TIMEOUT_MAX              0x0	u32 TxReqTimeOut;	BOOL TxFlow;		/*Tx flow control enable */	BOOL RxFlow;	BOOL OverrideTxServiceState;	/* TRUE: Overide, FALSE: Do not override 					   Use the new priority information					   of service state. It is not recommended					   to change but OSM can opt to do so */#define MAX_SERVICE_STATES  36	u8 TxServiceState[MAX_SERVICE_STATES];	/* Array element represent 'priority' 	 * and array index represents	 *  'Service state' e.g. 	 *  TxServiceState[3]=7; it means 	 *  Service state 3 is associated 	 *  with priority 7 of a Tx FIFO */	u64 TxIntrType;		/* Specifies if Tx Intr is UTILZ or PER_LIST type. *//* Rx Side */	u32 RxRingNum;		/*Number of receive rings */#define MAX_RX_RINGS 8#define MAX_RX_BLOCKS_PER_RING  150	rx_ring_config_t RxCfg[MAX_RX_RINGS];	/*Per-Rx Ring config */	BOOL RxVLANEnable;	/*TRUE: Strip off VLAN tag from the frame,				   FALSE: Don't strip off VLAN tag */#define HEADER_ETHERNET_II_802_3_SIZE 14#define HEADER_802_2_SIZE              3#define HEADER_SNAP_SIZE               5#define HEADER_VLAN_SIZE               4#define MIN_MTU                       46#define MAX_PYLD                    1500#define MAX_MTU                     (MAX_PYLD+18)#define MAX_MTU_VLAN                (MAX_PYLD+22)#define MAX_PYLD_JUMBO              9600#define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)#define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)	u32 MTU;		/*Maximum Payload */	BOOL JumboEnable;	/*Enable Jumbo frames recv/send */	BOOL OverrideRxServiceState;	/* TRUE: Overide, FALSE: Do not override 					   Use the new priority information					   of service state. It is not recommended					   to change but OSM can opt to do so */#define MAX_SERVICE_STATES  36