u8 RxServiceState[MAX_SERVICE_STATES];	/* Array element represent 'priority' 	 * and array index represents 	 * 'Service state'e.g. 	 * RxServiceState[3]=7; it means 	 * Service state 3 is associated 	 * with priority 7 of a Rx FIFO */	BOOL StatAutoRefresh;	/* When true, StatRefreshTime have valid value */	u32 StatRefreshTime;	/*Time for refreshing statistics */#define     STAT_TRSF_PER_1_SECOND      0x208D5};/* Structure representing MAC Addrs */typedef struct mac_addr {	u8 mac_addr[ETH_ALEN];} macaddr_t;/* Structure that represent every FIFO element in the BAR1 * Address location.  */typedef struct _TxFIFO_element {	u64 TxDL_Pointer;	u64 List_Control;#define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)#define TX_FIFO_FIRST_LIST             BIT(14)#define TX_FIFO_LAST_LIST              BIT(15)#define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)#define TX_FIFO_SPECIAL_FUNC           BIT(23)#define TX_FIFO_DS_NO_SNOOP            BIT(31)#define TX_FIFO_BUFF_NO_SNOOP          BIT(30)} TxFIFO_element_t;/* Tx descriptor structure */typedef struct _TxD {	u64 Control_1;/* bit mask */#define TXD_LIST_OWN_XENA       BIT(7)#define TXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))#define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))#define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)#define TXD_GATHER_CODE         (BIT(22) | BIT(23))#define TXD_GATHER_CODE_FIRST   BIT(22)#define TXD_GATHER_CODE_LAST    BIT(23)#define TXD_TCP_LSO_EN          BIT(30)#define TXD_UDP_COF_EN          BIT(31)#define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)#define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)	u64 Control_2;#define TXD_TX_CKO_CONTROL      (BIT(5)|BIT(6)|BIT(7))#define TXD_TX_CKO_IPV4_EN      BIT(5)#define TXD_TX_CKO_TCP_EN       BIT(6)#define TXD_TX_CKO_UDP_EN       BIT(7)#define TXD_VLAN_ENABLE         BIT(15)#define TXD_VLAN_TAG(val)       vBIT(val,16,16)#define TXD_INT_NUMBER(val)     vBIT(val,34,6)#define TXD_INT_TYPE_PER_LIST   BIT(47)#define TXD_INT_TYPE_UTILZ      BIT(46)#define TXD_SET_MARKER         vBIT(0x6,0,4)	u64 Buffer_Pointer;	u64 Host_Control;	/* reserved for host */} TxD_t;/* Rx descriptor structure */typedef struct _RxD_t {	u64 Host_Control;	/* reserved for host */	u64 Control_1;#define RXD_OWN_XENA            BIT(7)#define RXD_T_CODE              (BIT(12)|BIT(13)|BIT(14)|BIT(15))#define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)#define RXD_FRAME_PROTO_IPV4    BIT(27)#define RXD_FRAME_PROTO_IPV6    BIT(28)#define RXD_FRAME_PROTO_TCP     BIT(30)#define RXD_FRAME_PROTO_UDP     BIT(31)#define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)#define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)#define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)	u64 Control_2;#define MASK_BUFFER0_SIZE       vBIT(0xFFFF,0,16)#define SET_BUFFER0_SIZE(val)   vBIT(val,0,16)#define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)#define SET_VLAN_TAG(val)       vBIT(val,48,16)#define SET_NUM_TAG(val)       vBIT(val,16,32)#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))/*    #define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))  #define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))  */	u64 Buffer0_ptr;} RxD_t;/* Structure that represents the Rx descriptor block which contains  * 128 Rx descriptors. */typedef struct _RxD_block {#define MAX_RXDS_PER_BLOCK             127	RxD_t rxd[MAX_RXDS_PER_BLOCK];	u64 reserved_0;#define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */	u64 reserved_2_pNext_RxD_block;	/*@ Logical ptr to next */	u64 pNext_RxD_Blk_physical;	/* Buff0_ptr.					   In a 32 bit arch the upper 32 bits 					   should be 0 */} RxD_block_t;/* Structure which stores all the MAC control parameters *//* This structure stores the offset of the RxD in the ring  * from which the Rx Interrupt processor can start picking  * up the RxDs for processing. */typedef struct _rx_curr_get_info_t {	u32 block_index;	u32 offset;	u32 ring_len;} rx_curr_get_info_t;typedef rx_curr_get_info_t rx_curr_put_info_t;/* This structure stores the offset of the TxDl in the FIFO * from which the Tx Interrupt processor can start picking  * up the TxDLs for send complete interrupt processing. */typedef struct {	u32 offset;	u32 fifo_len;} tx_curr_get_info_t;typedef tx_curr_get_info_t tx_curr_put_info_t;/* Infomation related to the Tx and Rx FIFOs and Rings of Xena * is maintained in this structure. */typedef struct mac_info {/* rx side stuff */	u32 rxd_ring_mem_sz;	RxD_t *RxRing[MAX_RX_RINGS];	/* Logical Rx ring pointers */	dma_addr_t RxRing_Phy[MAX_RX_RINGS];	/* Put pointer info which indictes which RxD has to be replenished 	 * with a new buffer.	 */	rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];	/* Get pointer info which indictes which is the last RxD that was 	 * processed by the driver.	 */	rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];	u16 rmac_pause_time;	/* this will be used in receive function, this decides which ring would	   be processed first. eg: ring with priority value 0 (highest) should	   be processed first. 	   first 3 LSB bits represent ring number which should be processed 	   first, similarly next 3 bits represent next ring to be processed.	   eg: value of _rx_ring_pri_map = 0x0000 003A means 	   ring #2 would be processed first and #7 would be processed next	 */	u32 _rx_ring_pri_map;/* tx side stuff */	void *txd_list_mem;	/* orignal pointer to allocated mem */	dma_addr_t txd_list_mem_phy;	u32 txd_list_mem_sz;	/* logical pointer of start of each Tx FIFO */	TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];	/* logical pointer of start of TxDL which corresponds to each Tx FIFO */	TxD_t *txdl_start[MAX_TX_FIFOS];	/* Same as txdl_start but phy addr */	dma_addr_t txdl_start_phy[MAX_TX_FIFOS];/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/	tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];	tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];	u16 txdl_len;		/* length of a TxDL, same for all */	void *stats_mem;	/* orignal pointer to allocated mem */	dma_addr_t stats_mem_phy;	/* Physical address of the stat block */	u32 stats_mem_sz;	StatInfo_t *StatsInfo;	/* Logical address of the stat block */} mac_info_t;/* structure representing the user defined MAC addresses */typedef struct {	char addr[ETH_ALEN];	int usage_cnt;} usr_addr_t;/* Structure that holds the Phy and virt addresses of the Blocks */typedef struct rx_block_info {	RxD_t *block_virt_addr;	dma_addr_t block_dma_addr;} rx_block_info_t;/* Structure representing one instance of the NIC */typedef struct s2io_nic {#define MAX_MAC_SUPPORTED   16#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED	macaddr_t defMacAddr[MAX_MAC_SUPPORTED];	macaddr_t preMacAddr[MAX_MAC_SUPPORTED];	struct net_device_stats stats;	caddr_t bar0;	caddr_t bar1;	struct config_param config;	mac_info_t mac_control;	int high_dma_flag;	int device_close_flag;	int device_enabled_once;	char name[32];	struct tasklet_struct task;	atomic_t tasklet_status;	struct timer_list timer;	struct net_device *dev;	struct pci_dev *pdev;	u16 vendor_id;	u16 device_id;	u16 ccmd;	u32 cbar0_1;	u32 cbar0_2;	u32 cbar1_1;	u32 cbar1_2;	u32 cirq;	u8 cache_line;	u32 rom_expansion;	u16 pcix_cmd;	u32 config_space[256 / sizeof(u32)];	u32 irq;	atomic_t rx_bufs_left[MAX_RX_RINGS];	spinlock_t isr_lock;	spinlock_t tx_lock;#define PROMISC     1#define ALL_MULTI   2#define MAX_ADDRS_SUPPORTED 64	u16 usr_addr_count;	u16 mc_addr_count;	usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];	u16 m_cast_flg;	u16 all_multi_pos;	u16 promisc_flg;	u16 tx_pkt_count;	u16 rx_pkt_count;	u16 tx_err_count;	u16 rx_err_count;#if DEBUG_ON	u64 rxpkt_bytes;	u64 txpkt_bytes;	int int_cnt;	int rxint_cnt;	int txint_cnt;	u64 rxpkt_cnt;#endif	/*  Place holders for the virtual and physical addresses of 	 *  all the Rx Blocks	 */	struct rx_block_info	 rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];	int block_count[MAX_RX_RINGS];	int pkt_cnt[MAX_RX_RINGS];	/*  Id timer, used to blink NIC to physically identify NIC. */	struct timer_list id_timer;	/*  Restart timer, used to restart NIC if the device is stuck and	 *  a schedule task that will set the correct Link state once the 	 *  NIC's PHY has stabilized after a state change.	 */#ifdef INIT_TQUEUE	struct tq_struct rst_timer_task;	struct tq_struct set_link_task;#else	struct work_struct rst_timer_task;	struct work_struct set_link_task;#endif	/* Flag that can be used to turn on or turn off the Rx checksum 	 * offload feature.	 */	int rx_csum;	/*  after blink, the adapter must be restored with original 	 *  values.	 */	u64 adapt_ctrl_org;	/* Last known link state. */	u16 last_link_state;#define	LINK_DOWN	1#define	LINK_UP		2} nic_t;#define RESET_ERROR 1;#define CMD_ERROR   2;/* Default Tunable parameters of the NIC. */#define DEFAULT_FIFO_LEN 4096#define SMALL_RXD_CNT	40 * (MAX_RXDS_PER_BLOCK+1)#define LARGE_RXD_CNT	100 * (MAX_RXDS_PER_BLOCK+1)/*  OS related system calls */#ifndef readqstatic inline u64 readq(void *addr){	u64 ret = 0;	ret = readl(addr + 4);	ret <<= 32;	ret |= readl(addr);	return ret;}#endif#ifndef writeqstatic inline void writeq(u64 val, void *addr){	writel((u32) (val), addr);	writel((u32) (val >> 32), (addr + 4));}#endif/*  Interrupt related values of Xena */#define ENABLE_INTRS    1#define DISABLE_INTRS   2/*  Highest level interrupt blocks */#define TX_PIC_INTR     (0x0001<<0)#define TX_DMA_INTR     (0x0001<<1)#define TX_MAC_INTR     (0x0001<<2)#define TX_XGXS_INTR    (0x0001<<3)#define TX_TRAFFIC_INTR (0x0001<<4)#define RX_PIC_INTR     (0x0001<<5)#define RX_DMA_INTR     (0x0001<<6)#define RX_MAC_INTR     (0x0001<<7)#define RX_XGXS_INTR    (0x0001<<8)#define RX_TRAFFIC_INTR (0x0001<<9)#define MC_INTR         (0x0001<<10)#define ENA_ALL_INTRS    (   TX_PIC_INTR     | \                            TX_DMA_INTR     | \                            TX_MAC_INTR     | \                            TX_XGXS_INTR    | \                            TX_TRAFFIC_INTR | \                            RX_PIC_INTR     | \                            RX_DMA_INTR     | \                            RX_MAC_INTR     | \                            RX_XGXS_INTR    | \                            RX_TRAFFIC_INTR | \                            MC_INTR )/*  Interrupt masks for the general interrupt mask register */#define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL#define TXPIC_INT_M         BIT(0)#define TXDMA_INT_M         BIT(1)#define TXMAC_INT_M         BIT(2)#define TXXGXS_INT_M        BIT(3)#define TXTRAFFIC_INT_M     BIT(8)#define PIC_RX_INT_M        BIT(32)#define RXDMA_INT_M         BIT(33)#define RXMAC_INT_M         BIT(34)#define MC_INT_M            BIT(35)#define RXXGXS_INT_M        BIT(36)#define RXTRAFFIC_INT_M     BIT(40)/*  PIC level Interrupts TODO*//*  DMA level Inressupts */#define TXDMA_PFC_INT_M     BIT(0)    /*  PFC block interrupts */#define PFC_MISC_ERR_1      BIT(0)	/* Interrupt to indicate FIFO full *//* * Prototype declaration. */static int __devinit s2io_init_nic(struct pci_dev *pdev,				   const struct pci_device_id *pre);static void __devexit s2io_rem_nic(struct pci_dev *pdev);static int initSharedMem(struct s2io_nic *sp);static void freeSharedMem(struct s2io_nic *sp);static int initNic(struct s2io_nic *nic);#ifndef CONFIG_S2IO_NAPIstatic void rxIntrHandler(struct s2io_nic *sp);#endifstatic void txIntrHandler(struct s2io_nic *sp);static void alarmIntrHandler(struct s2io_nic *sp);static int s2io_starter(void);void s2io_closer(void);static void s2io_tx_watchdog(struct net_device *dev);static void s2io_tasklet(unsigned long dev_addr);static void s2io_set_multicast(struct net_device *dev);static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);void s2io_link(nic_t * sp, int link);void s2io_reset(nic_t * sp);#ifdef CONFIG_S2IO_NAPIstatic int s2io_poll(struct net_device *dev, int *budget);#endifstatic void s2io_init_pci(nic_t * sp);int s2io_set_mac_addr(struct net_device *dev, u8 * addr);static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);static int verify_xena_quiescence(u64 val64, int flag);static struct ethtool_ops netdev_ethtool_ops;#endif				/* _S2IO_H */