/************************************************************************ * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com) * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice.  This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. ************************************************************************/#ifndef _REGS_H#define _REGS_H#define TBD 0typedef struct _XENA_dev_config {/* Convention: mHAL_XXX is mask, vHAL_XXX is value *//* General Control-Status Registers */	u64 general_int_status;#define GEN_INTR_TXPIC             BIT(0)#define GEN_INTR_TXDMA             BIT(1)#define GEN_INTR_TXMAC             BIT(2)#define GEN_INTR_TXXGXS            BIT(3)#define GEN_INTR_TXTRAFFIC         BIT(8)#define GEN_INTR_RXPIC             BIT(32)#define GEN_INTR_RXDMA             BIT(33)#define GEN_INTR_RXMAC             BIT(34)#define GEN_INTR_MC                BIT(35)#define GEN_INTR_RXXGXS            BIT(36)#define GEN_INTR_RXTRAFFIC         BIT(40)#define GEN_ERROR_INTR             GEN_INTR_TXPIC | GEN_INTR_RXPIC | \                                   GEN_INTR_TXDMA | GEN_INTR_RXDMA | \                                   GEN_INTR_TXMAC | GEN_INTR_RXMAC | \                                   GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \                                   GEN_INTR_MC	u64 general_int_mask;	u8 unused0[0x100 - 0x10];	u64 sw_reset;/* XGXS must be removed from reset only once. */#define SW_RESET_XENA              vBIT(0xA5,0,8)#define SW_RESET_FLASH             vBIT(0xA5,8,8)#define SW_RESET_EOI               vBIT(0xA5,16,8)#define SW_RESET_ALL               (SW_RESET_XENA     |   \                                    SW_RESET_FLASH    |   \                                    SW_RESET_EOI)/* The SW_RESET register must read this value after a successful reset. */#define	SW_RESET_RAW_VAL			0xA5000000	u64 adapter_status;#define ADAPTER_STATUS_TDMA_READY          BIT(0)#define ADAPTER_STATUS_RDMA_READY          BIT(1)#define ADAPTER_STATUS_PFC_READY           BIT(2)#define ADAPTER_STATUS_TMAC_BUF_EMPTY      BIT(3)#define ADAPTER_STATUS_PIC_QUIESCENT       BIT(5)#define ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)#define ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)#define ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)#define ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)#define ADAPTER_STATUS_MC_DRAM_READY       BIT(24)#define ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)#define ADAPTER_STATUS_M_PLL_LOCK          BIT(30)#define ADAPTER_STATUS_P_PLL_LOCK          BIT(31)	u64 adapter_control;#define ADAPTER_CNTL_EN                    BIT(7)#define ADAPTER_EOI_TX_ON                  BIT(15)#define ADAPTER_LED_ON                     BIT(23)#define ADAPTER_UDPI(val)                  vBIT(val,36,4)#define ADAPTER_WAIT_INT                   BIT(48)#define ADAPTER_ECC_EN                     BIT(55)	u64 serr_source;#define SERR_SOURCE_PIC					BIT(0)#define SERR_SOURCE_TXDMA				BIT(1)#define SERR_SOURCE_RXDMA				BIT(2)#define SERR_SOURCE_MAC                 BIT(3)#define SERR_SOURCE_MC                  BIT(4)#define SERR_SOURCE_XGXS                BIT(5)#define	SERR_SOURCE_ANY					(SERR_SOURCE_PIC		| \										SERR_SOURCE_TXDMA	| \										SERR_SOURCE_RXDMA	| \										SERR_SOURCE_MAC		| \										SERR_SOURCE_MC      | \										SERR_SOURCE_XGXS)	u8 unused_0[0x800 - 0x120];/* PCI-X Controller registers */	u64 pic_int_status;	u64 pic_int_mask;#define PIC_INT_TX                     BIT(0)#define PIC_INT_FLSH                   BIT(1)#define PIC_INT_MDIO                   BIT(2)#define PIC_INT_IIC                    BIT(3)#define PIC_INT_GPIO                   BIT(4)#define PIC_INT_RX                     BIT(32)	u64 txpic_int_reg;	u64 txpic_int_mask;#define PCIX_INT_REG_ECC_SG_ERR                BIT(0)#define PCIX_INT_REG_ECC_DB_ERR                BIT(1)#define PCIX_INT_REG_FLASHR_R_FSM_ERR          BIT(8)#define PCIX_INT_REG_FLASHR_W_FSM_ERR          BIT(9)#define PCIX_INT_REG_INI_TX_FSM_SERR           BIT(10)#define PCIX_INT_REG_INI_TXO_FSM_ERR           BIT(11)#define PCIX_INT_REG_TRT_FSM_SERR              BIT(13)#define PCIX_INT_REG_SRT_FSM_SERR              BIT(14)#define PCIX_INT_REG_PIFR_FSM_SERR             BIT(15)#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR      BIT(21)#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR       BIT(23)#define PCIX_INT_REG_INI_RX_FSM_SERR           BIT(48)#define PCIX_INT_REG_RA_RX_FSM_SERR            BIT(50)/*#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR      BIT(52)#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR       BIT(54)#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR     BIT(58)*/	u64 txpic_alarms;	u64 rxpic_int_reg;	u64 rxpic_int_mask;	u64 rxpic_alarms;	u64 flsh_int_reg;	u64 flsh_int_mask;#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR         BIT(63)#define PIC_FLSH_INT_REG_ERR                   BIT(62)	u64 flash_alarms;	u64 mdio_int_reg;	u64 mdio_int_mask;#define MDIO_INT_REG_MDIO_BUS_ERR              BIT(0)#define MDIO_INT_REG_DTX_BUS_ERR               BIT(8)#define MDIO_INT_REG_LASI                      BIT(39)	u64 mdio_alarms;	u64 iic_int_reg;	u64 iic_int_mask;#define IIC_INT_REG_BUS_FSM_ERR                BIT(4)#define IIC_INT_REG_BIT_FSM_ERR                BIT(5)#define IIC_INT_REG_CYCLE_FSM_ERR              BIT(6)#define IIC_INT_REG_REQ_FSM_ERR                BIT(7)#define IIC_INT_REG_ACK_ERR                    BIT(8)	u64 iic_alarms;	u8 unused4[0x08];	u64 gpio_int_reg;	u64 gpio_int_mask;	u64 gpio_alarms;	u8 unused5[0x38];	u64 tx_traffic_int;#define TX_TRAFFIC_INT_n(n)                    BIT(n)	u64 tx_traffic_mask;	u64 rx_traffic_int;#define RX_TRAFFIC_INT_n(n)                    BIT(n)	u64 rx_traffic_mask;/* PIC Control registers */	u64 pic_control;#define PIC_CNTL_RX_ALARM_MAP_1                BIT(0)#define PIC_CNTL_SHARED_SPLITS(n)              vBIT(n,11,4)	u64 swapper_ctrl;#define SWAPPER_CTRL_PIF_R_FE                  BIT(0)#define SWAPPER_CTRL_PIF_R_SE                  BIT(1)#define SWAPPER_CTRL_PIF_W_FE                  BIT(8)#define SWAPPER_CTRL_PIF_W_SE                  BIT(9)#define SWAPPER_CTRL_TXP_FE                    BIT(16)#define SWAPPER_CTRL_TXP_SE                    BIT(17)#define SWAPPER_CTRL_TXD_R_FE                  BIT(18)#define SWAPPER_CTRL_TXD_R_SE                  BIT(19)#define SWAPPER_CTRL_TXD_W_FE                  BIT(20)#define SWAPPER_CTRL_TXD_W_SE                  BIT(21)#define SWAPPER_CTRL_TXF_R_FE                  BIT(22)#define SWAPPER_CTRL_TXF_R_SE                  BIT(23)#define SWAPPER_CTRL_RXD_R_FE                  BIT(32)#define SWAPPER_CTRL_RXD_R_SE                  BIT(33)#define SWAPPER_CTRL_RXD_W_FE                  BIT(34)#define SWAPPER_CTRL_RXD_W_SE                  BIT(35)#define SWAPPER_CTRL_RXF_W_FE                  BIT(36)#define SWAPPER_CTRL_RXF_W_SE                  BIT(37)#define SWAPPER_CTRL_XMSI_FE                   BIT(40)#define SWAPPER_CTRL_XMSI_SE                   BIT(41)#define SWAPPER_CTRL_STATS_FE                  BIT(48)#define SWAPPER_CTRL_STATS_SE                  BIT(49)	u64 pif_rd_swapper_fb;#define IF_RD_SWAPPER_FB                            0x0123456789ABCDEF	u64 scheduled_int_ctrl;#define SCHED_INT_CTRL_TIMER_EN                BIT(0)#define SCHED_INT_CTRL_ONE_SHOT                BIT(1)#define SCHED_INT_CTRL_INT2MSI                 TBD#define SCHED_INT_PERIOD                       TBD	u64 txreqtimeout;#define TXREQTO_VAL(val)						vBIT(val,0,32)#define TXREQTO_EN								BIT(63)	u64 statsreqtimeout;#define STATREQTO_VAL(n)                       TBD#define STATREQTO_EN                           BIT(63)	u64 read_retry_delay;	u64 read_retry_acceleration;	u64 write_retry_delay;	u64 write_retry_acceleration;	u64 xmsi_control;	u64 xmsi_access;	u64 xmsi_address;	u64 xmsi_data;	u64 rx_mat;	u8 unused6[0x8];	u64 tx_mat0_7;	u64 tx_mat8_15;	u64 tx_mat16_23;	u64 tx_mat24_31;	u64 tx_mat32_39;	u64 tx_mat40_47;	u64 tx_mat48_55;	u64 tx_mat56_63;	u8 unused_1[0x10];	/* Automated statistics collection */	u64 stat_cfg;#define STAT_CFG_STAT_EN           BIT(0)#define STAT_CFG_ONE_SHOT_EN       BIT(1)#define STAT_CFG_STAT_NS_EN        BIT(8)#define STAT_CFG_STAT_RO           BIT(9)#define STAT_TRSF_PER(n)           TBD#define	PER_SEC					   0x208d5#define	SET_UPDT_PERIOD(n)		   vBIT((PER_SEC*n),32,32)	u64 stat_addr;	/* General Configuration */	u64 mdio_control;	u64 dtx_control;	u64 i2c_control;#define	I2C_CONTROL_DEV_ID(id)		vBIT(id,1,3)#define	I2C_CONTROL_ADDR(addr)		vBIT(addr,5,11)#define	I2C_CONTROL_BYTE_CNT(cnt)	vBIT(cnt,22,2)#define	I2C_CONTROL_READ			BIT(24)#define	I2C_CONTROL_NACK			BIT(25)#define	I2C_CONTROL_CNTL_START		vBIT(0xE,28,4)#define	I2C_CONTROL_CNTL_END(val)	(val & vBIT(0x1,28,4))#define	I2C_CONTROL_GET_DATA(val)	(u32)(val & 0xFFFFFFFF)#define	I2C_CONTROL_SET_DATA(val)	vBIT(val,32,32)	u64 gpio_control;#define GPIO_CTRL_GPIO_0		BIT(8)	u8 unused7[0x600];/* TxDMA registers */	u64 txdma_int_status;	u64 txdma_int_mask;#define TXDMA_PFC_INT                  BIT(0)#define TXDMA_TDA_INT                  BIT(1)#define TXDMA_PCC_INT                  BIT(2)#define TXDMA_TTI_INT                  BIT(3)#define TXDMA_LSO_INT                  BIT(4)#define TXDMA_TPA_INT                  BIT(5)#define TXDMA_SM_INT                   BIT(6)	u64 pfc_err_reg;	u64 pfc_err_mask;	u64 pfc_err_alarm;	u64 tda_err_reg;	u64 tda_err_mask;	u64 tda_err_alarm;	u64 pcc_err_reg;	u64 pcc_err_mask;	u64 pcc_err_alarm;	u64 tti_err_reg;	u64 tti_err_mask;	u64 tti_err_alarm;	u64 lso_err_reg;	u64 lso_err_mask;	u64 lso_err_alarm;	u64 tpa_err_reg;	u64 tpa_err_mask;	u64 tpa_err_alarm;	u64 sm_err_reg;	u64 sm_err_mask;	u64 sm_err_alarm;	u8 unused8[0x100 - 0xB8];/* TxDMA arbiter */	u64 tx_dma_wrap_stat;/* Tx FIFO controller */#define X_MAX_FIFOS                        8#define X_FIFO_MAX_LEN                     0x1FFF	/*8191 */	u64 tx_fifo_partition_0;#define TX_FIFO_PARTITION_EN               BIT(0)#define TX_FIFO_PARTITION_0_PRI(val)       vBIT(val,5,3)#define TX_FIFO_PARTITION_0_LEN(val)       vBIT(val,19,13)#define TX_FIFO_PARTITION_1_PRI(val)       vBIT(val,37,3)#define TX_FIFO_PARTITION_1_LEN(val)       vBIT(val,51,13  )	u64 tx_fifo_partition_1;#define TX_FIFO_PARTITION_2_PRI(val)       vBIT(val,5,3)#define TX_FIFO_PARTITION_2_LEN(val)       vBIT(val,19,13)#define TX_FIFO_PARTITION_3_PRI(val)       vBIT(val,37,3)#define TX_FIFO_PARTITION_3_LEN(val)       vBIT(val,51,13)	u64 tx_fifo_partition_2;#define TX_FIFO_PARTITION_4_PRI(val)       vBIT(val,5,3)#define TX_FIFO_PARTITION_4_LEN(val)       vBIT(val,19,13)#define TX_FIFO_PARTITION_5_PRI(val)       vBIT(val,37,3)#define TX_FIFO_PARTITION_5_LEN(val)       vBIT(val,51,13)	u64 tx_fifo_partition_3;#define TX_FIFO_PARTITION_6_PRI(val)       vBIT(val,5,3)#define TX_FIFO_PARTITION_6_LEN(val)       vBIT(val,19,13)#define TX_FIFO_PARTITION_7_PRI(val)       vBIT(val,37,3)#define TX_FIFO_PARTITION_7_LEN(val)       vBIT(val,51,13)#define TX_FIFO_PARTITION_PRI_0                 0	/* highest */#define TX_FIFO_PARTITION_PRI_1                 1#define TX_FIFO_PARTITION_PRI_2                 2#define TX_FIFO_PARTITION_PRI_3                 3#define TX_FIFO_PARTITION_PRI_4                 4#define TX_FIFO_PARTITION_PRI_5                 5#define TX_FIFO_PARTITION_PRI_6                 6#define TX_FIFO_PARTITION_PRI_7                 7	/* lowest */	u64 tx_w_round_robin_0;	u64 tx_w_round_robin_1;	u64 tx_w_round_robin_2;	u64 tx_w_round_robin_3;	u64 tx_w_round_robin_4;	u64 tti_command_mem;#define TTI_CMD_MEM_WE                     BIT(7)#define TTI_CMD_MEM_STROBE_NEW_CMD         BIT(15)#define TTI_CMD_MEM_STROBE_BEING_EXECUTED  BIT(15)#define TTI_CMD_MEM_OFFSET(n)              vBIT(n,26,6)	u64 tti_data1_mem;#define TTI_DATA1_MEM_TX_TIMER_VAL(n)      vBIT(n,6,26)#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n)    vBIT(n,38,2)#define TTI_DATA1_MEM_TX_TIMER_AC_EN       BIT(38)#define TTI_DATA1_MEM_TX_TIMER_CI_EN       BIT(39)#define TTI_DATA1_MEM_TX_URNG_A(n)         vBIT(n,41,7)#define TTI_DATA1_MEM_TX_URNG_B(n)         vBIT(n,49,7)#define TTI_DATA1_MEM_TX_URNG_C(n)         vBIT(n,57,7)	u64 tti_data2_mem;#define TTI_DATA2_MEM_TX_UFC_A(n)          vBIT(n,0,16)#define TTI_DATA2_MEM_TX_UFC_B(n)          vBIT(n,16,16)#define TTI_DATA2_MEM_TX_UFC_C(n)          vBIT(n,32,16)#define TTI_DATA2_MEM_TX_UFC_D(n)          vBIT(n,48,16)/* Tx Protocol assist */	u64 tx_pa_cfg;#define TX_PA_CFG_IGNORE_FRM_ERR           BIT(1)#define TX_PA_CFG_IGNORE_SNAP_OUI          BIT(2)#define TX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)#define	TX_PA_CFG_IGNORE_L2_ERR			   BIT(6)/* Recent add, used only debug purposes. */	u64 pcc_enable;