/**************************************************************/
//
// Copyright (c) Texas Instruments 2005. All rights reserved.
//
/***************************************************************
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT
LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR 
FITNESS FOR A PARTICULAR PURPOSE.

Module Name:	
		HostSPIComm.H

Abstract:	
		This header file contains the functions to setup 
		the Intel Mainstone (PXA27x) /PENIRQ interrupt to 
		interface with the /PENIRQ of TI's TSC2046 device. 
		This is an example for using the interrupt of a
		host processor with TI's TSC2046 Windows CE 5.0
		touch screen driver.

Functions:
  
Revision History:
Rev 0.0		Original Release	WXF	9-30-2005

***************************************************************/

#ifndef __HostSPIComm_H__
#define __HostSPIComm_H__

#ifdef __cplusplus
extern "C" {
#endif 

//
//--------------------------------------------------------------
// Defines Intel PXA27x (Bulverde) Processor SSP(SPI) Registers
//--------------------------------------------------------------
//
// defines for SSP Control Register 0 (SSCR0)
#define SCR_1300_KHZ	0x00900	// 1.3Mbps (13MHz Internal Clock)
#define SCR_590_KHZ		0x01500	// 590.9KHz			
#define SCR_200_KHZ		0x04000	// 200KHz			
#define SCR_50_KHZ		0x0FF00	// 50.78KHz
#define SCR_3_KHZ		0xFFF00 // 3.174KHz

#define SSE_DISABLE		0x00
#define SSE_ENABLE		0x80

#define ECS_INTERNAL	0x00
#define ECS_EXTERNAL	0x40

#define FRF_MOTOROLA	0x00
#define FRF_TI			0x10
#define FRF_MICROWIRE	0x20
#define FRF_PROG		0x30

#define DSS_8_BIT		0x07
#define DSS_16_BIT		0x0F

// defines for SSP Control Register 1 (SSCR1)
#define RFT_ZERO		0x0000
#define RFT_SEVEN		0x1C00
#define RFT_FIFTEEN		0x3C00

#define TFT_ZERO		0x0000
#define TFT_SEVEN		0x01C0

#define MWDS_8_BIT		0x00
#define MWDS_16_BIT		0x20

#define SPH_FULL_DELAY	0x00
#define SPH_HALF_DELAY	0x10

#define SPO_IDLE_LOW	0x00
#define SPO_IDLE_HIGH	0x08

#define LBM_DISABLE		0x00
#define LBM_ENABLE		0x04

#define TIE_DISABLE		0x00
#define TIE_ENABLE		0x02

#define RIE_DISABLE		0x00
#define RIE_ENABLE		0x01

// defines for SSP Status Register (SSSR)
#define ROR_NORMAL		0x00
#define ROR__OVERRUN	0x80

#define RFS_NORMAL		0x00
#define RFS_IRQ_THROWN	0x40

#define TFS_NORMAL		0x00
#define TFS_IRQ_THROWN	0x20

#define BSY_IDLE		0x00
#define BSY_BUSY		0x10

#define RNE_EMPTY		0x00
#define RNE_NOT_EMPTY	0x08

#define TNF_FULL		0x00
#define TNF_NOT_FULL	0x04

//
//-------------------------------------------------------------------
// Defines Intel PXA27x (Bulverde) Processor GPIO Registers for SPI
//-------------------------------------------------------------------
//
// defines for GPIO Direction Register (GPDR0)
#define GPIO_23_SCLK	(0x1 << 23)
#define GPIO_24_SFRM	(0x1 << 24)
#define GPIO_25_MOSI	(0x1 << 25)
#define GPIO_26_MISO	(0x1 << 26)

// defines for GPIO Alternate Function Register (GAFR0_U)
#define GPIO_23_AF2_SSPSCLK	(0x2 << 14)
#define GPIO_24_AF2_SSPSFRM	(0x2 << 16)
#define GPIO_25_AF2_SSPTXD	(0x2 << 18)
#define GPIO_26_AF1_SSPRXD	(0x1 << 20)

//
//--------------------------------------------------------------
// Debugging Routines
//--------------------------------------------------------------
//
void DumpRegsGPIO(void);  
void DumpRegsSSP(void);
void DumpRegsClock(void);

//
//--------------------------------------------------------------
// Processor Depended Layer Routines for PXA27x 
//--------------------------------------------------------------
//
BOOL HWDeallocateSPIResources(void);
BOOL HWAllocateSPIResources(void);
BOOL HWInitSPI(BOOL InPowerHandle);
void HWDeinitSPI(BOOL InPowerHandle);
void HWStartFrame(void);
void HWStopFrame(void);
void HWSPIWriteWord(UINT8 iWord);
UINT8 HWSPIReadWord(void);
BOOL HWSPITxBusy(void);
BOOL HWSPIRxBusy(void);
BOOL HWSPIFIFONotEmpty(void);

void HWWait(UINT32 microSecs);

#ifdef __cplusplus
}
#endif 

#endif // __HostSPIComm_H__

//**************************************************************
//
// END of FILE
//
//**************************************************************
////////////////////////////////////////////////////////////////