/**************************************************************/
//
// Copyright (c) Texas Instruments 2005.  All rights reserved.
//
/***************************************************************
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT
LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR 
FITNESS FOR A PARTICULAR PURPOSE.

Module Name:	
		HostSPIComm.C

Abstract:	
		This module contains the functions for host processor to 
		communicate with the TSC2046 device through an SPI bus, 
		which is host-processor dependent (there the Intel's 
		Bulverde processor is used as the example).

Functions:
  
Revision History:
Rev 0.0		Original Release	WXF	9-30-2005

***************************************************************/

#include	<windows.h>
#include 	<bsp.h>
#include	<xllp_ost.h>
#include	<HostSPIComm.h>

//
//--------------------------------------------------------------
// Local Variables
//--------------------------------------------------------------
//
volatile BULVERDE_GPIO_REG	 *g_pGPIORegs  = NULL;
volatile BULVERDE_SSP_REG	 *g_pSSPRegs   = NULL;
volatile BULVERDE_OST_REG	 *g_pOSTRegs   = NULL;
volatile BULVERDE_CLKMGR_REG *g_pClockRegs = NULL;

//
//--------------------------------------------------------------
// Debugging Routines
//--------------------------------------------------------------
//
void DumpRegsGPIO(void)
{
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPDR0=%X\r\n"),g_pGPIORegs->GPDR0));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPDR1=%X\r\n"),g_pGPIORegs->GPDR1));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPDR2=%X\r\n"),g_pGPIORegs->GPDR2));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPDR3=%X\r\n"),g_pGPIORegs->GPDR3));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPLR0=%X\r\n"),g_pGPIORegs->GPLR0));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPLR1=%X\r\n"),g_pGPIORegs->GPLR1));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPLR2=%X\r\n"),g_pGPIORegs->GPLR2));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GPLR3=%X\r\n"),g_pGPIORegs->GPLR3));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR0_L=%X\r\n"),g_pGPIORegs->GAFR0_L));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR0_U=%X\r\n"),g_pGPIORegs->GAFR0_U));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR1_L=%X\r\n"),g_pGPIORegs->GAFR1_L));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR1_U=%X\r\n"),g_pGPIORegs->GAFR1_U));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR2_L=%X\r\n"),g_pGPIORegs->GAFR2_L));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR2_U=%X\r\n"),g_pGPIORegs->GAFR2_U));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR3_L=%X\r\n"),g_pGPIORegs->GAFR3_L));	
	RETAILMSG(1,(TEXT("g_pGPIORegs->GAFR3_U=%X\r\n"),g_pGPIORegs->GAFR3_U));	
}

void DumpRegsSSP(void)
{
	RETAILMSG(1,(TEXT("g_pSSPRegs->sscr0=%X\r\n"),g_pSSPRegs->sscr0));	
	RETAILMSG(1,(TEXT("g_pSSPRegs->sscr1=%X\r\n"),g_pSSPRegs->sscr1));	
	RETAILMSG(1,(TEXT("g_pSSPRegs->ssr=%X\r\n"),g_pSSPRegs->ssr));	
}	

void DumpRegsClock(void)
{
	RETAILMSG(1,(TEXT("g_pClockRegs->cccr=%X\r\n"),g_pClockRegs->cccr));	
	RETAILMSG(1,(TEXT("g_pClockRegs->cken=%X\r\n"),g_pClockRegs->cken));	
	RETAILMSG(1,(TEXT("g_pClockRegs->oscc=%X\r\n"),g_pClockRegs->oscc));	
	RETAILMSG(1,(TEXT("g_pClockRegs->ccsr=%X\r\n"),g_pClockRegs->ccsr));	
}

//
//--------------------------------------------------------------
// Processor Depended Layer Routines for PXA27x 
//--------------------------------------------------------------
//
///////
// Function: BOOL HWDeallocateSPIResources
// Purpose:  Clean up host for any PDD-allocated SPI resources
///////
BOOL HWDeallocateSPIResources(void)
{
	if (g_pGPIORegs)
    {
        VirtualFree((void *)g_pGPIORegs, 0, MEM_RELEASE);
        g_pGPIORegs = NULL;
    }
    if (g_pSSPRegs)
    {
        VirtualFree((void *)g_pSSPRegs, 0, MEM_RELEASE);
        g_pSSPRegs = NULL;
    }
	if (g_pOSTRegs)
    {
        VirtualFree((void *)g_pOSTRegs, 0, MEM_RELEASE);
        g_pOSTRegs = NULL;
    }
    if (g_pClockRegs)
    {
        VirtualFree((void *)g_pClockRegs, 0, MEM_RELEASE);
        g_pClockRegs = NULL;
    }
    return(TRUE);
}

///////
// Function: BOOL HWAllocateSPIResources(void)
// Purpose:  Allocate SPI resources on host
///////
BOOL HWAllocateSPIResources(void)
{
    PHYSICAL_ADDRESS RegPA;
    if (g_pGPIORegs == NULL)
    {
        RegPA.QuadPart = BULVERDE_BASE_REG_PA_GPIO;
        g_pGPIORegs = (volatile BULVERDE_GPIO_REG *) MmMapIoSpace(RegPA, 0x400, FALSE);
    }
    if (g_pSSPRegs == NULL)
    {
        RegPA.QuadPart = BULVERDE_BASE_REG_PA_SSP1;
        g_pSSPRegs = (volatile BULVERDE_SSP_REG *) MmMapIoSpace(RegPA, 0x400, FALSE);
    }
    if (g_pOSTRegs == NULL)
    {
        RegPA.QuadPart = BULVERDE_BASE_REG_PA_OST;
        g_pOSTRegs = (volatile BULVERDE_OST_REG *) MmMapIoSpace(RegPA, 0x400, FALSE);
    }
    if (g_pClockRegs == NULL)
    {
        RegPA.QuadPart = BULVERDE_BASE_REG_PA_CLKMGR;
        g_pClockRegs = (volatile BULVERDE_CLKMGR_REG *) MmMapIoSpace(RegPA, 0x400, FALSE);
    }
    if (!g_pGPIORegs || !g_pSSPRegs || !g_pOSTRegs || !g_pClockRegs)
    {
        RETAILMSG(1, (TEXT("ERROR: Failed to allocate SPI resources (Error=%u).\r\n"), GetLastError()));
        HWDeallocateSPIResources();
        return(FALSE);
    } 
    return(TRUE);
}

//
//-------------------------------------------------------------------
// Function: void HWInitSPI(BOOL InPowerHandle)
// Purpose:  This function must be called from the power handler of the respective drivers
//           using this library. This function will configure the GPIO pins according to 
//           the functionality shown in the table below
//
//		Signals			Pin#		Direction		Alternate Function
//		SSPSCLK			GP23		output				2
//		SSPSFRM			GP24		output				0
//		SSPTXD			GP25		output				2
//		SSPRXD			GP26		input				1
//		SSPSCLKEN		GP27		input				2
//-------------------------------------------------------------------
BOOL HWInitSPI(BOOL InPowerHandle)
{
	RETAILMSG(1,(TEXT("Setup Host GPIO & SSP for an SPI Interface... \r\n")));

	// disable Unit clock
	g_pClockRegs->cken &= ~XLLP_CLKEN_SSP1;

	// disable SSP1
	g_pSSPRegs->sscr0 &= ~SSE_ENABLE;

	if (g_pGPIORegs)
	{
		// Set up the GPIO24=SFRM = 1 (GPSR0)
		g_pGPIORegs->GPSR0 |= ( GPIO_24_SFRM );

		// Program direction of the GPIOs (GPDR0)
		// (GPIO23/24/25 as outputs and GPIO26 as input) 
		g_pGPIORegs->GPDR0 |= GPIO_23_SCLK;
		g_pGPIORegs->GPDR0 |= GPIO_24_SFRM;
		g_pGPIORegs->GPDR0 |= GPIO_25_MOSI;
		g_pGPIORegs->GPDR0 &= ~GPIO_26_MISO;

		// Program GPIO alternate function register (GAFR0_U)
		g_pGPIORegs->GAFR0_U &= 0xFFC03FFF;
		g_pGPIORegs->GAFR0_U |= GPIO_23_AF2_SSPSCLK;
//		g_pGPIORegs->GAFR0_U |= GPIO_24_AF2_SSPSFRM;
		g_pGPIORegs->GAFR0_U |= GPIO_25_AF2_SSPTXD;
		g_pGPIORegs->GAFR0_U |= GPIO_26_AF1_SSPRXD;
	}
	else
	{
		RETAILMSG(1, (TEXT("HWInitSPI - Fail to Get GPIOs \r\n")));
		return (FALSE);
	}

	// Set up SSP registers (when disabled SSP)
	// set up SSP control register 0 and 1
	g_pSSPRegs->sscr0 = (SCR_590_KHZ |
						SSE_DISABLE | 
		                ECS_INTERNAL | 
						FRF_MOTOROLA | 
						DSS_8_BIT );
	g_pSSPRegs->sscr1 = (RFT_ZERO |
						TFT_ZERO | 
						SPH_FULL_DELAY | 
						SPO_IDLE_LOW | 
		                LBM_DISABLE | 
						TIE_DISABLE | 
						RIE_DISABLE );
	// Enable SSP last
	g_pSSPRegs->sscr0 |= SSE_ENABLE;

	// enable SPI1 Unit clock
    g_pClockRegs->cken |= XLLP_CLKEN_SSP1;

	DumpRegsGPIO();
	DumpRegsSSP();
	DumpRegsClock();
	return (TRUE);
}

///////
// Function: HWDeinitSPI Routine 
// Purpose:  disable SSP operation using the SSCR/SSE register
///////
void HWDeinitSPI(BOOL InPowerHandle)
{
	g_pSSPRegs->sscr0 &= ~SSE_ENABLE;
}

///////
// Function: HWStartFrame Routine
// Purpose:  This routine sets /SS pin low to active SPI
///////
void HWStartFrame(void)
{
	g_pGPIORegs->GPCR0 |= GPIO_24_SFRM;
}

///////
// Function: HWStopFrame Routine
// Purpose:  This routine sets /SS pin high to disable SPI
///////
void HWStopFrame(void)
{			
	g_pGPIORegs->GPSR0 |= GPIO_24_SFRM;
}

///////
// Function: HWSPIWriteWord Routine
// Purpose:  Write an 8-bits word through SPI
///////
void HWSPIWriteWord(UINT8 iWord)
{
	while((g_pSSPRegs->ssr & TNF_NOT_FULL) == 0){;}
	g_pSSPRegs->ssdr = iWord;
}

///////
// Function: HWSPIReadWord Routine
// Purpose:  Read an 8-bits word through SPI
///////
UINT8 HWSPIReadWord(void)
{
	while((g_pSSPRegs->ssr & RNE_NOT_EMPTY) == 0){;}
	return ( (UINT8)g_pSSPRegs->ssdr );
}

///////
// Function: HWSPITxBusy Routine
// Purpose:  Check if SPI TX is busy 
///////
BOOL HWSPITxBusy(void)
{
	// actually it's SPI bus (Tx/RX) busy
	return ((g_pSSPRegs->ssr) & BSY_BUSY); 
}

///////
// Function: HWSPIRxBusy Routine
// Purpose:  Check if SPI RX is busy
///////
BOOL HWSPIRxBusy(void)
{
	return FALSE;
}

///////
// Function: HWSPIFIFONotEmpty Routine
// Purpose:  check if FIFO has not empty
///////
BOOL HWSPIFIFONotEmpty(void)
{
	return ((g_pSSPRegs->ssr) & RNE_NOT_EMPTY);
}

///////
// Function: HWWait routine
// Purpose:  wait some time (in micro-seconds)
///////
void HWWait(UINT32 microSecs) 
{
    XllpOstDelayMicroSeconds((P_XLLP_OST_T) g_pOSTRegs, microSecs);
}

//
//--------------------------------------------------------------
// End of HostSPIComm.C Functions
//--------------------------------------------------------------
//
//**************************************************************
//
// END of FILE
//
//**************************************************************
////////////////////////////////////////////////////////////////