#ifndef _LPC21XX_H_
#define _LPC21XX_H_

//-- Flash accelerator
#define rMAMCR    (*(volatile unsigned int *) 0xE01FC000)
#define rMAMTIM   (*(volatile unsigned int *) 0xE01FC004)


//-- Watchdog Timer (32 bit data bus)
#define rWDMOD    (*(volatile unsigned int *) 0xE0000000)
#define rWDTC     (*(volatile unsigned int *) 0xE0000004)
#define rWDFEED   (*(volatile unsigned int *) 0xE0000008)
#define rWDTV     (*(volatile unsigned int *) 0xE000000C)

//-- Timer 0 (32 bit data bus)
#define rTIMER0_IR   (*(volatile unsigned int *) 0xE0004000) // intr reg
#define rTIMER0_TCR  (*(volatile unsigned int *) 0xE0004004) // ctrl
#define rTIMER0_TC   (*(volatile unsigned int *) 0xE0004008) // counter
#define rTIMER0_PR   (*(volatile unsigned int *) 0xE000400C) // prescale reg
#define rTIMER0_PC   (*(volatile unsigned int *) 0xE0004010) // prescale cnt
#define rTIMER0_MCR  (*(volatile unsigned int *) 0xE0004014) // match ctrl
#define rTIMER0_MR0  (*(volatile unsigned int *) 0xE0004018) // match reg0
#define rTIMER0_MR1  (*(volatile unsigned int *) 0xE000401C) // match reg1
#define rTIMER0_MR2  (*(volatile unsigned int *) 0xE0004020) // match reg2
#define rTIMER0_MR3  (*(volatile unsigned int *) 0xE0004024) // match reg3
#define rTIMER0_CCR  (*(volatile unsigned int *) 0xE0004028) // capt ctrl
#define rTIMER0_CR0  (*(volatile unsigned int *) 0xE000402C) // capt reg0
#define rTIMER0_CR1  (*(volatile unsigned int *) 0xE0004030) // capt reg1
#define rTIMER0_CR2  (*(volatile unsigned int *) 0xE0004034) // capt reg2
#define rTIMER0_CR3  (*(volatile unsigned int *) 0xE0004038) // capt reg3
#define rTIMER0_EMR  (*(volatile unsigned int *) 0xE000403C) // ext match reg

//-- Timer 1 (32 bit data bus)
#define rTIMER1_IR   (*(volatile unsigned int *) 0xE0008000) // Interrupt register
#define rTIMER1_TCR  (*(volatile unsigned int *) 0xE0008004) // Timer Control register
#define rTIMER1_TC   (*(volatile unsigned int *) 0xE0008008) // Timer Counter
#define rTIMER1_PR   (*(volatile unsigned int *) 0xE000800C) // Prescale register
#define rTIMER1_PC   (*(volatile unsigned int *) 0xE0008010) // Prescale Counter
#define rTIMER1_MCR  (*(volatile unsigned int *) 0xE0008014) // Match Control register
#define rTIMER1_MR0  (*(volatile unsigned int *) 0xE0008018) // Match reg0
#define rTIMER1_MR1  (*(volatile unsigned int *) 0xE000801C) // Match reg1
#define rTIMER1_MR2  (*(volatile unsigned int *) 0xE0008020) // Match reg2
#define rTIMER1_MR3  (*(volatile unsigned int *) 0xE0008024) // Match reg3
#define rTIMER1_CCR  (*(volatile unsigned int *) 0xE0008028) // Capture Control register
#define rTIMER1_CR0  (*(volatile unsigned int *) 0xE000802C) // Capt reg0
#define rTIMER1_CR1  (*(volatile unsigned int *) 0xE0008030) // Capt reg1
#define rTIMER1_CR2  (*(volatile unsigned int *) 0xE0008034) // Capt reg2
#define rTIMER1_CR3  (*(volatile unsigned int *) 0xE0008038) // Capt reg3
#define rTIMER1_EMR  (*(volatile unsigned int *) 0xE000803C) // External Match register

//-- UART0 (8 bit data bus)
#define rUART0_RBR   (*(volatile unsigned int *) 0xE000C000) // receive buffer-RO
#define rUART0_THR   (*(volatile unsigned int *) 0xE000C000) // transmit hold buffer-WO
#define rUART0_IER   (*(volatile unsigned int *) 0xE000C004) // interrupt enable
#define rUART0_IIR   (*(volatile unsigned int *) 0xE000C008) // interrupt id-RO
#define rUART0_FCR   (*(volatile unsigned int *) 0xE000C008) // fifo control-WO
#define rUART0_LCR   (*(volatile unsigned int *) 0xE000C00C) // line control
#define rUART0_LSR   (*(volatile unsigned int *) 0xE000C014) // line status-RO
#define rUART0_SCR   (*(volatile unsigned int *) 0xE000C01C) // scratchpad
#define rUART0_DLL   (*(volatile unsigned int *) 0xE000C000) // divisor latch LSB
#define rUART0_DLM   (*(volatile unsigned int *) 0xE000C004) // divisor latch MSB

//-- UART1 (8 bit data bus)
#define rUART1_RBR   (*(volatile unsigned int *) 0xE0010000) // receive buffer-RO
#define rUART1_THR   (*(volatile unsigned int *) 0xE0010000) // transmit hold buffer-WO
#define rUART1_IER   (*(volatile unsigned int *) 0xE0010004) // interrupt enable
#define rUART1_IIR   (*(volatile unsigned int *) 0xE0010008) // interrupt id-RO
#define rUART1_FCR   (*(volatile unsigned int *) 0xE0010008) // fifo control-WO
#define rUART1_LCR   (*(volatile unsigned int *) 0xE001000C) // line control
#define rUART1_MCR   (*(volatile unsigned int *) 0xE0010010) // modem control
#define rUART1_LSR   (*(volatile unsigned int *) 0xE0010014) // line status-RO
#define rUART1_MSR   (*(volatile unsigned int *) 0xE0010018) // modem status-RO
#define rUART1_SCR   (*(volatile unsigned int *) 0xE001001C) // scratchpad
#define rUART1_DLL   (*(volatile unsigned int *) 0xE0010000) // divisor latch LSB
#define rUART1_DLM   (*(volatile unsigned int *) 0xE0010004) // divisor latch MSB

//-- PWM0 (32 bit data bus)
#define rPWM0_IR     (*(volatile unsigned int *) 0xE0014000) // intr reg
#define rPWM0_TCR    (*(volatile unsigned int *) 0xE0014004) // timer ctrl
#define rPWM0_TC     (*(volatile unsigned int *) 0xE0014008) // timer counter
#define rPWM0_PR     (*(volatile unsigned int *) 0xE001400C) // prescale reg
#define rPWM0_PC     (*(volatile unsigned int *) 0xE0014010) // prescale count
#define rPWM0_MCR    (*(volatile unsigned int *) 0xE0014014) // match ctrl reg
#define rPWM0_MR0    (*(volatile unsigned int *) 0xE0014018) // match reg0
#define rPWM0_MR1    (*(volatile unsigned int *) 0xE001401C) // match reg1
#define rPWM0_MR2    (*(volatile unsigned int *) 0xE0014020) // match reg2
#define rPWM0_MR3    (*(volatile unsigned int *) 0xE0014024) // match reg3
#define rPWM0_CCR    (*(volatile unsigned int *) 0xE0014028) // capt ctrl
#define rPWM0_CR0    (*(volatile unsigned int *) 0xE001402C) // capt reg0
#define rPWM0_CR1    (*(volatile unsigned int *) 0xE0014030) // capt reg1
#define rPWM0_CR2    (*(volatile unsigned int *) 0xE0014034) // capt reg2
#define rPWM0_CR3    (*(volatile unsigned int *) 0xE0014038) // capt reg3
#define rPWM0_EMR    (*(volatile unsigned int *) 0xE001403C) // ext match reg
#define rPWM0_MR4    (*(volatile unsigned int *) 0xE0014040) // match reg4
#define rPWM0_MR5    (*(volatile unsigned int *) 0xE0014044) // match reg5
#define rPWM0_MR6    (*(volatile unsigned int *) 0xE0014048) // match reg6
#define rPWM0_PCR    (*(volatile unsigned int *) 0xE001404C) // pwm ctrl reg
#define rPWM0_LER    (*(volatile unsigned int *) 0xE0014050) // latch enable reg

//-- PWM1 (32 bit data bus) -- addresses reserved
//--                   from base + 0x18000 to 0xE00018050
//-- I2C (8/16 bit data bus)

#define  rI2C_I2CONSET   (*(volatile unsigned int *) 0xE001C000) // ctrl set reg
#define  rI2C_I2STAT     (*(volatile unsigned int *) 0xE001C004) // status reg-RO
#define  rI2C_I2DAT      (*(volatile unsigned int *) 0xE001C008) // data reg
#define  rI2C_I2ADR      (*(volatile unsigned int *) 0xE001C00C) // addr reg
#define  rI2C_I2SCLH     (*(volatile unsigned int *) 0xE001C010) // scl dutycycle hi
#define  rI2C_I2SCLL     (*(volatile unsigned int *) 0xE001C014) // scl dutycycle lo
#define  rI2C_I2CONCLR   (*(volatile unsigned int *) 0xE001C018) // ctrl clr reg

//-- SPI (8 bit data bus) (spec shows 0xE0020000 - 0xE0023FFF)
#define  rSPI_SPCR   (*(volatile unsigned int *) 0xE0020000) // Control Register
#define  rSPI_SPSR   (*(volatile unsigned int *) 0xE0020004) // Status Register
#define  rSPI_SPDR   (*(volatile unsigned int *) 0xE0020008) // Data Register
#define  rSPI_SPCCR  (*(volatile unsigned int *) 0xE002000C) // Clock Counter Register
#define  rSPI_SPTCR  (*(volatile unsigned int *) 0xE0020010) // Test Control Register
#define  rSPI_SPTSR  (*(volatile unsigned int *) 0xE0020014) // Test Status Register
#define  rSPI_SPTOR  (*(volatile unsigned int *) 0xE0020018) // Test Observe Register
#define  rSPI_SPINT  (*(volatile unsigned int *) 0xE002001C) // SPI interrupt flag

//-- RTC (32 bit data bus)
#define rRTC_ILR           (*(volatile unsigned int *) 0xE0024000) // Interrupt Location Register