/*
 *  Copyright 2004 by SEED Incorporated.
 *  All rights reserved. Property of SEED Incorporated.
 */

/*
 *  ======== seeddm642.h ========
 *
 */

#ifndef EVMDM642_
#define EVMDM642_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <csl_i2c.h>
#include <csl_gpio.h>

/*
 *  Note:  Bit definitions for each register field
 *         needs to be supplied here for the CPLD
 *	       and other board periperals.
 */

/* Compatability definitions */
#define NULL                 0

/* CPLD address definitions */
#define SEEDDM642_CPLD_BASE       0x90080000
/*FLASH address definitions*/
#define EVMDM642_FPGASDRAM_BASE   0x80000000
/*ATA address definitions*/
#define SEEDDM642_ATACS0          0xA0000000
#define SEEDDM642_ATACS1          0xA0000020

/* CPLD Register Indices */
#define SEEDDM642_IOOUT       0x10 //write only
#define SEEDDM642_IOINPUT     0x10 //read only
#define SEEDDM642_FLASHPAGE   0x11 //write only
#define SEEDDM642_ATASTAUS    0x11 //read only	
#define SEEDDM642_UARTSET     0x12 //write only
#define SEEDDM642_PLLSET      0x13 //write only
#define SEEDDM642_ESAMW       0x14 //writte only
#define SEEDDM642_ESAMR       0x14 //read only


/* Read an 8-bit value from a CPLD register */
Uint8 SEEDDM642_rget(Int16 regnum);

/* Write an 8-bit value to a CPLD register */
void SEEDDM642_rset(Int16 regnum, Uint8 regval);

/* Spin in a delay loop for delay iterations */
void SEEDDM642_wait(Uint32 delay);

/* Spin in a delay loop for delay microseconds */
void SEEDDM642_waitusec(Uint32 delay);

/* Send a configuration file to the FPGA */
void EVMDM642_loadFpga(Uint32 fpgaaddr);

#ifdef __cplusplus
}
#endif

#endif