?? butterfly1.vhd
字號:
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:integer:=17; --乘法數位寬
w1:integer:=9; --c+s和的位寬
w:integer:=8); --輸入位寬
port(clk:std_logic;
are_in,aim_in,c_in,bre_in,bim_in:in std_logic_vector(w-1 downto 0); --8位輸入
cps_in,cms_in:in std_logic_vector(w1-1 downto 0);--9位系數
dre_out,dim_out,ere_out,eim_out:out std_logic_vector(w-1 downto 0)); --8位結果
end butterfly1;
architecture bf of butterfly1 is
signal dif_re,dif_im:std_logic_vector(w-1 downto 0);
signal are,aim,bre,bim:integer range -128 to 127;
signal c:std_logic_vector(w-1 downto 0);
signal cps,cms:std_logic_vector(w1-1 downto 0); --輸入系數
signal cre,cim:std_logic_vector(w1-1 downto 0);
component ccmul
generic(w2:positive; --乘法數位寬
w1:positive; --c+s和的位寬
w:positive); --輸入位寬
port(clk:std_logic; --輸出寄存器的時鐘
x_in,y_in,c_in:in std_logic_vector(w-1 downto 0);
cps_in,cms_in:in std_logic_vector(w1-1 downto 0);
r_out,i_out:out std_logic_vector(w-1 downto 0));
end component;
begin
process --整數和輸入寄存在FF中
begin
wait until clk='1';
are<=conv_integer(are_in);
aim<=conv_integer(aim_in);
bre<=conv_integer(bre_in);
bim<=conv_integer(bim_in);
c<=c_in; --從內存中加載cos
cps<=cps_in; --從內存中加載cos+sin
cms<=cms_in; --從內存中加載cos-sin
dre_out<=conv_std_logic_vector((are+bre)/2,w);
dim_out<=conv_std_logic_vector((aim+bim)/2,w);
end process;
process(are,bre,aim,bim)
begin
dif_re<=conv_std_logic_vector((are-bre)/2,8);
dif_im<=conv_std_logic_vector((aim-bim)/2,w);
end process;
--實例化復數旋轉因子
ccmul_1:ccmul
generic map(w2=>w,w1=>w1,w=>w)
port map(clk=>clk,x_in=>dif_re,y_in=>dif_im,c_in=>c,cps_in=>cps,cms_in=>cms,r_out=>ere_out,i_out=>eim_out);
end bf;
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