;**************************************************************************************************
;*
;* Copyright (C) ART Limited, 2006. All rights reserved.
;* 
;* File:          Cstartup.s
;* Programmed by: allan
;* Data:          2006.12.18
;* 
;**************************************************************************************************/
                INCLUDE         config.inc

;-------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.

; 復位向量。通常INTVEC段被鏈接到0地址，為程序調試方便，也可以將其放在其他地址。
;-------------------------------------------------------------------------------
                AREA            reset, CODE, READONLY
                CODE32

;-------------------------------------------------------------------------------
;- Remove any semihosting support
;--------------------------------
;- The C runtime library is the IO functions provided by the semihosting.
;- They are generally costly in code and unused as the debugger is not 
;- connected to the target. 
;- Must be removed if using the embedded C library is used.
;-------------------------------------------------------------------------------
;- Define "__main" to ensure that C runtime system is not linked

                EXPORT          __main
__main

;-------------------------------------------------------------------------------
;- Define the entry point
;------------------------
;- Note on the link address and the Remap command.
;- In order to guarantee that the non position-independant code (the ARM linker 
;- armlink doesn't generate position-independant code) can work on the ARM, 
;- it must be linked at address at which it expects to run. 
;- So the -ro-base must be used to define the link address as the base 
;- address of the flash.
;- In this startup example, we use 0x100 0000 as base address. That's flash 
;- address for all AT91 Evaluation Boards.
;-------------------------------------------------------------------------------
                ENTRY

;-------------------------------------------------------------------------------
;- Exception vectors
;-------------------------------------------------------------------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exeption occurs before start application to infinite loop.

;- 異常向量。向量地址可以從0地址或RAM地址讀取，必須采用相對尋址方式以保證跳轉指令
;- 的合法性。如果異常發生在重新映射之前，將導致死循環。
;-------------------------------------------------------------------------------
start
                B       InitReset            ;-0x00 復位句柄
undefvec
                B       undefvec             ;-0x04 未定義指令
swivec
                B       swivec               ;-0x08 軟件中斷
pabtvec
                B       pabtvec              ;-0x0C 預取中止
dabtvec
                B       dabtvec              ;-0x10 數據中止
rsvdvec
                B       rsvdvec              ;-0x14 保留
irqvec
                B       irq                  ;-0x18 IRQ
fiqvec
                B       fiq                  ;-0x1C FIQ



;------------------------------------------------------------------------------
;- 函數：fiq
;- 說明：fiq控制中斷句柄
;- 調用函數：AIC_FVR[interrupt]
;------------------------------------------------------------------------------
fiq
;- 由于FIQ還未被承認，故切換管理/用戶模式，允許用戶堆棧訪問C代碼
;- Save and r0 in FIQ_Register
       mov      r9, r0
       ldr      r0, [r8, #AIC_FVR]
       msr      CPSR_c, #0xd3

;- Save scratch/used registers and LR in User Stack
       stmfd    sp!, {r1-r3, r12, lr}

;- Branch to the routine pointed by the AIC_FVR
       mov      r14, pc
       bx       r0

;- Restore scratch/used registers and LR from User Stack
       ldmia    sp!, {r1-r3, r12, lr}

;- Leave Interrupts disabled and switch back in FIQ mode
       msr      CPSR_c, #0xd1

;- Restore the R0 ARM_MODE_SVC register
       mov      r0, r9

;- Restore the Program Counter using the LR_fiq directly in the PC
       subs     pc, lr, #4


;------------------------------------------------------------------------------
;- Manage exception     : The exception must be ensure in ARM mode
;- Treatments           : IRQ Controller Interrupt Handler.
;- Called Functions     : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
irq

;-------------------------
;- Manage Exception Entry
;-------------------------
;- Adjust and save LR_irq in IRQ stack
       sub      lr, lr, #4
       stmfd    sp!, {lr}

;- Save r0 and SPSR (need to be saved for nested interrupt)
       mrs      r14, SPSR
       stmfd    sp!, {r0, r14}

;- Write in the IVR to support Protect Mode
       ldr      r14, =AT91C_BASE_AIC
       ldr      r0 , [r14, #AIC_IVR]
       str      r14, [r14, #AIC_IVR]

;- Enable Interrupt and Switch in Supervisor Mode
       msr      CPSR_c, #0x13

;- Save scratch/used registers and LR in User Stack
       stmfd    sp!, {r1-r3, r12, r14}

;----------------------------------------------
;- Branch to the routine pointed by the AIC_IVR
;----------------------------------------------
       mov      r14, pc
       bx       r0

;----------------------------------------------
;- Manage Exception Exit
;----------------------------------------------
;- Restore scratch/used registers and LR from User Stack
       ldmia    sp!, {r1-r3, r12, r14}

;- Disable Interrupt and switch back in IRQ mode
       msr      CPSR_c, #0x92

;- Mark the End of Interrupt on the AIC
       ldr      r14, =AT91C_BASE_AIC
       str      r14, [r14, #AIC_EOICR]

;- Restore SPSR_irq and r0 from IRQ stack
       ldmia    sp!, {r0, r14}
       msr      SPSR_cxsf, r14

;- Restore adjusted  LR_irq from IRQ stack directly in the PC
       ldmia    sp!, {pc}^


;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;------------------------------------------------------------------------------
;- Retrieve end of RAM address
__iramend       EQU   INTRAMEND_REMAP        ;- Segment begin
       EXTERN   AT91F_LowLevelInit
InitReset
       ldr      r13, =__iramend              ;- Temporary stack
       ldr      r0, =AT91F_LowLevelInit
       mov      lr, pc
       bx       r0

;------------------------------------------------------------------------------
;- Top of Stack Definition
;------------------------------------------------------------------------------
;- Interrupt and Supervisor Stack are located at the top of internal memory in
;- order to speed the exception handling context saving and restoring.
;- ARM_MODE_SVC (App, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
;- 3 words to be saved per interrupt priority level
IRQ_STACK_SIZE          EQU     (3*8*4)

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;------------------------------------------------------------------------------
        ldr     r0, =__iramend

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
        msr     CPSR_c, #0xd1
;- Init the FIQ register
        ldr     r8, =AT91C_BASE_AIC

;- Set up Interrupt Mode and set IRQ Mode Stack
        msr     CPSR_c, #0xd2
        mov     r13, r0
        sub     r0, r0, #IRQ_STACK_SIZE

;- Enable interrupt & Set Supervisor Mode Stack
        msr     CPSR_c, #0x13
        mov     r13, r0

;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------
;- Following labels are automatically generated by the linker. 
;- RO: Read-only = the code
;- RW: Read Write = the data pre-initialized and zero-initialized.
;- ZI: Zero-Initialized.
;- Pre-initialization values are located after the code area in the image.
;- Zero-initialized datas are mapped after the pre-initialized.
;- Note on the Data position : 
;- If using the ARMSDT, when no -rw-base option is used for the linker, the 
;- data area is mapped after the code. You can map the data either in internal
;- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
;- Note also that to improve the code density, the pre_initialized data must 
;- be limited to a minimum.
;------------------------------------------------------------------------------
                IMPORT      |Image$$RO$$Limit|      ; End of ROM code
                IMPORT      |Image$$RW$$Base|       ; Base of RAM to initialise
                IMPORT      |Image$$ZI$$Base|       ; Base and limit of area
                IMPORT      |Image$$ZI$$Limit|      ; To zero initialise

                ldr         r0, =|Image$$RO$$Limit|
                ldr         r1, =|Image$$RW$$Base|
                ldr         r3, =|Image$$ZI$$Base|
                cmp         r0, r1
                beq         NoRW
LoopRw          cmp         r1, r3                  ; Copy init data
                ldrcc       r2, [r0], #4
                strcc       r2, [r1], #4
                bcc         LoopRw
NoRW            ldr         r1, =|Image$$ZI$$Limit|
                mov         r2, #0
LoopZI          cmp         r3, r1                  ; Zero init
                strcc       r2, [r3], #4
                bcc         LoopZI

;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb 
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors 
;------------------------------------------------------------------------------
                IMPORT      main

                ldr         r0, =main
                mov         lr, pc
                bx          r0

;------------------------------------------------------------------------------
;- Exception Vectors
;------------------------------------------------------------------------------
        CODE32    ; Always ARM mode after exeption
        EXPORT    AT91F_Default_FIQ_handler
        EXPORT    AT91F_Default_IRQ_handler
        EXPORT    AT91F_Spurious_handler

AT91F_Default_FIQ_handler
        b         AT91F_Default_FIQ_handler

AT91F_Default_IRQ_handler
        b         AT91F_Default_IRQ_handler

AT91F_Spurious_handler
        b         AT91F_Spurious_handler

;------------------------------------------------------------------------------
        EXPORT  ARMDisableInt
ARMDisableInt
        STMFD   sp!, {r0}
        MRS     r0, CPSR
        ORR     r0, r0, #0x80
        MSR     CPSR_cxsf, r0
        LDMFD   sp!, {r0}
        MOV     pc, lr

        EXPORT  ARMEnableInt
ARMEnableInt    
        STMFD   sp!, {r0}
        MRS     r0, CPSR
        BIC     r0, r0, #0x80
        MSR     CPSR_cxsf, r0
        LDMFD   sp!, {r0}
        MOV     pc, lr

;------------------------------------------------------------------------------
            END