///////////////////////////////////////////////////////////////////////////////
//
//  (C) Copyright 1995 - 1998 OSR Open Systems Resources, Inc.
//	All Rights Reserved
//      Based on a previous work by Microsoft Corporation
//      Copyright (c) 1991, 1992, 1993  Microsoft Corporation
//
//    This sofware is supplied for instructional purposes only.
//
//      OSR Open Systems Resources, Inc. (OSR) expressly disclaims any warranty
//      for this software.  THIS SOFTWARE IS PROVIDED  "AS IS" WITHOUT WARRANTY
//      OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION,
//      THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR
//      PURPOSE.  THE ENTIRE RISK ARISING FROM THE USE OF THIS SOFTWARE REMAINS
//      WITH YOU.  OSR's entire liability and your exclusive remedy shall not
//      exceed the price paid for this material.  In no event shall OSR or its
//      suppliers be liable for any damages whatsoever (including, without
//      limitation, damages for loss of business profit, business interruption,
//      loss of business information, or any other pecuniary loss) arising out
//      of the use or inability to use this software, even if OSR has been
//      advised of the possibility of such damages.  Because some states/
//      jurisdictions do not allow the exclusion or limitation of liability for
//      consequential or incidental damages, the above limitation may not apply
//      to you.
//
//    This driver is the example Programmed I/O device driver that
//    accompanies the book Windows NT Device Driver Development, by
//    Peter Viscarola and W. Anthony Mason, (c) 1998 OSR Open Systems
//    Resources, Inc. and published by MacMillan Technical Publishing
//    ISBN 1578700582.  
//
//	MODULE:
//
//		$Workfile: utils.c $
//
//	ABSTRACT:
//
//    This module contains some general utilities
//
//	AUTHOR:
//
//		Open Systems Resources, Inc.
// 
//	REVISION:   
//
//
///////////////////////////////////////////////////////////////////////////////
#include "ntddk.h"                      // main NT include
#include "ntdddisk.h"                   // disk driver IOCTL definitions
#include "hw.h"                         // the access macro/definitions
#include "ide.h"                        // IDE structure definitions



///////////////////////////////////////////////////////////////////////////////
//
//	IdeWaitControllerReady
//
//    This routine waits for the controller to turn off the BUSY bit in the CSR
//
//	INPUTS:
//
//    ControllerData       - controller information
//    MsDelay              - number of ms to delay each time
//    NumDelay             - number of times to delay
//
//	OUTPUTS:
//	
//    None.
//
//	RETURNS:
//
//    STATUS_SUCCESS if BUSY bit was OFF, otherwise STATUS_TIMEOUT
//
//      IRQL:
//
//    >= IRQL_DISPATCH_LEVEL
//
//	NOTES:
//
///////////////////////////////////////////////////////////////////////////////

NTSTATUS
IdeWaitControllerReady(PCONTROLLER_DATA ControllerData,
                    ULONG MsDelay,
                    ULONG NumDelay)

{
    ULONG loopCount = 0;

    //
    // Loop, trying to read the CSR and test for the BUSY bit to be set
    // 

    while ((READ_PORT_UCHAR(
        ControllerData->ControllerAddress + STATUS_REGISTER) &
        BUSY_STATUS)  &&
        (loopCount++ < NumDelay)) 
    {

        //
        // if the BUSY bit is NOT set, the stall the processor 
        //

        KeStallExecutionProcessor(MsDelay);

    }

    //
    // If we've tried to read the CSR NumDelay times, then we assume
    // failure and we return the STATUS_IO_TIMEOUT, otherwise we've exited
    // the loop early and the CSR BUSY bit must be ON, so return STATUS_SUCCESS
    //

    if (loopCount == NumDelay) 
    {

#if DBG
        DbgPrint(
            "IdeWaitControllerReady: ERROR: controller not ready\n");
#endif
        return STATUS_IO_TIMEOUT;

    } 
    else {

            return STATUS_SUCCESS;

    }
}


///////////////////////////////////////////////////////////////////////////////
//
//	IdeWaitControllerBusy
//
//    This routine waits for the controller to turn ON the BUSY bit in the CSR
//
//	INPUTS:
//
//    ControllerData       - controller information
//    MsDelay              - number of ms to delay each time
//    NumDelay             - number of times to delay
//
//	OUTPUTS:
//	
//    None.
//
//	RETURNS:
//
//    STATUS_SUCCESS if BUSY bit was turned ON, otherwise STATUS_TIMEOUT
//
//      IRQL:
//
//    >= IRQL_DISPATCH_LEVEL
//
//	NOTES:
//
///////////////////////////////////////////////////////////////////////////////

NTSTATUS
IdeWaitControllerBusy(
PUCHAR StatusRegisterAddress,
ULONG MsDelay,
ULONG NumDelay
)

{
    ULONG loopCount = 0;

    //
    // Loop, trying to read the CSR and test for the BUSY bit NOT to be set
    // 

    while (!(READ_PORT_UCHAR(StatusRegisterAddress) & BUSY_STATUS)  &&
        (loopCount++ < NumDelay)) 
    {

        //
        // if the BUSY bit is set, the stall the processor 
        //

        KeStallExecutionProcessor(MsDelay);

    }

    //
    // If we've tried to read the CSR NumDelay times, then we assume
    // failure and we return the STATUS_IO_TIMEOUT, otherwise we've exited
    // the loop early and the CSR BUSY bit must be OFF, so return STATUS_SUCCESS
    //

    if (loopCount == NumDelay) 
    {

#if DBG
        DbgPrint(
            "IdeWaitControllerBusy: ERROR: controller not busy\n");
#endif
        return STATUS_IO_TIMEOUT;

    } 
    else {

            return STATUS_SUCCESS;

    }
}