.equiv CH0SB2, 0x000A
         .equiv CH0SB1, 0x0009
         .equiv CH0SB0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv CH123NA1, 0x0007
         .equiv CH123NA0, 0x0006
         .equiv CH123SA, 0x0005
         .equiv CH0NA, 0x0004
         .equiv CH0SA3, 0x0003
         .equiv CH0SA2, 0x0002
         .equiv CH0SA1, 0x0001
         .equiv CH0SA0, 0x0000

;------------------------------------------------------------------------------
;     ADPCFG : A/D Port Configuration Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PCFG15, 0x000F
         .equiv PCFG14, 0x000E
         .equiv PCFG13, 0x000D
         .equiv PCFG12, 0x000C
         .equiv PCFG11, 0x000B
         .equiv PCFG10, 0x000A
         .equiv PCFG9, 0x0009
         .equiv PCFG8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv PCFG7, 0x0007
         .equiv PCFG6, 0x0006
         .equiv PCFG5, 0x0005
         .equiv PCFG4, 0x0004
         .equiv PCFG3, 0x0003
         .equiv PCFG2, 0x0002
         .equiv PCFG1, 0x0001
         .equiv PCFG0, 0x0000

;------------------------------------------------------------------------------
;     ADCSSL : A/D Input Scan Select Register ;SFR present only in 12-bit ADC
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv CSSL15, 0x000F
         .equiv CSSL14, 0x000E
         .equiv CSSL13, 0x000D
         .equiv CSSL12, 0x000C
         .equiv CSSL11, 0x000B
         .equiv CSSL10, 0x000A
         .equiv CSSL9, 0x0009
         .equiv CSSL8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv CSSL7, 0x0007
         .equiv CSSL6, 0x0006
         .equiv CSSL5, 0x0005
         .equiv CSSL4, 0x0004
         .equiv CSSL3, 0x0003
         .equiv CSSL2, 0x0002
         .equiv CSSL1, 0x0001
         .equiv CSSL0, 0x0000


;==============================================================================
;
; 13.  Port B: General Purpose I/O Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 13a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv TRISBL, _TRISB                  ; See all SFR descriptions in
                                                ;  sub-section below
         .equiv PORTBL, _PORTB
         .equiv LATBL, _LATB


;------------------------------------------------------------------------------
; 13b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TRISB : Port B Data Direction Control Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TRISB5, 0x0005
         .equiv TRISB4, 0x0004
         .equiv TRISB3, 0x0003
         .equiv TRISB2, 0x0002
         .equiv TRISB1, 0x0001
         .equiv TRISB0, 0x0000

;------------------------------------------------------------------------------
;     PORTB : Read Port B Pin / Write Port B Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv RB5, 0x0005
         .equiv RB4, 0x0004
         .equiv RB3, 0x0003
         .equiv RB2, 0x0002
         .equiv RB1, 0x0001
         .equiv RB0, 0x0000

;------------------------------------------------------------------------------
;     LATB : Read / Write Port B Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv LATB5, 0x0005
         .equiv LATB4, 0x0004
         .equiv LATB3, 0x0003
         .equiv LATB2, 0x0002
         .equiv LATB1, 0x0001
         .equiv LATB0, 0x0000

;==============================================================================
;
; 14.  Port C: General Purpose I/O Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 14a. SFR Definitions
;------------------------------------------------------------------------------
                                                ; See all SFR descriptions in
         .equiv TRISCH, _TRISC+1                ;  sub-section below
         .equiv PORTCH, _PORTC+1
         .equiv LATCH, _LATC+1

;------------------------------------------------------------------------------
; 14b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TRISC : Port C Data Direction Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv TRISC15, 0x000F
         .equiv TRISC14, 0x000E
         .equiv TRISC13, 0x000D

;------------------------------------------------------------------------------
;     PORTC : Read Port C Pin / Write Port C Latch Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv RC15, 0x000F
         .equiv RC14, 0x000E
         .equiv RC13, 0x000D

;------------------------------------------------------------------------------
;     LATC : Read / Write Port C Latch Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv LATC15, 0x000F
         .equiv LATC14, 0x000E
         .equiv LATC13, 0x000D

;==============================================================================
;
; 15.  Port D: General Purpose I/O Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 15a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv TRISDL, _TRISD                  ; See all SFR descriptions in
                                                ;  sub-section below
         .equiv PORTDL, _PORTD
         .equiv LATDL, _LATD


;------------------------------------------------------------------------------
; 15b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TRISD : Port D Data Direction Control Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TRISD1, 0x0001
         .equiv TRISD0, 0x0000

;------------------------------------------------------------------------------
;     PORTD : Read Port D Pin / Write Port D Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv RD1, 0x0001
         .equiv RD0, 0x0000

;------------------------------------------------------------------------------
;     LATD : Read / Write Port D Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv LATD1, 0x0001
         .equiv LATD0, 0x0000

;==============================================================================
;
; 16.  Port E: General Purpose I/O Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 16a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv TRISEL, _TRISE                  ; See all SFR descriptions in
         .equiv TRISEH, _TRISE+1                ;  sub-section below
         .equiv PORTEL, _PORTE
         .equiv PORTEH, _PORTE+1
         .equiv LATEL, _LATE
         .equiv LATEH, _LATE+1

;------------------------------------------------------------------------------
; 16b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TRISE : Port E Data Direction Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv TRISE8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TRISE5, 0x0005
         .equiv TRISE4, 0x0004
         .equiv TRISE3, 0x0003
         .equiv TRISE2, 0x0002
         .equiv TRISE1, 0x0001
         .equiv TRISE0, 0x0000

;------------------------------------------------------------------------------
;     PORTE : Read Port E Pin / Write Port E Latch Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv RE8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv RE5, 0x0005
         .equiv RE4, 0x0004
         .equiv RE3, 0x0003
         .equiv RE2, 0x0002
         .equiv RE1, 0x0001
         .equiv RE0, 0x0000

;------------------------------------------------------------------------------
;     LATE : Read / Write Port E Latch Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv LATE8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv LATE5, 0x0005
         .equiv LATE4, 0x0004
         .equiv LATE3, 0x0003
         .equiv LATE2, 0x0002
         .equiv LATE1, 0x0001
         .equiv LATE0, 0x0000

;==============================================================================
;
; 17.  Port F: General Purpose I/O Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 17a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv TRISFL, _TRISF                  ; See all SFR descriptions in
                                                ;  sub-section below
         .equiv PORTFL, _PORTF
         .equiv LATFL, _LATF


;------------------------------------------------------------------------------
; 17b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TRISF : Port F Data Direction Control Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TRISF3, 0x0003
         .equiv TRISF2, 0x0002

;------------------------------------------------------------------------------
;     PORTF : Read Port F Pin / Write Port F Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv RF3, 0x0003
         .equiv RF2, 0x0002

;------------------------------------------------------------------------------
;     LATF : Read / Write Port F Latch Register
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv LATF3, 0x0003
         .equiv LATF2, 0x0002


;==============================================================================
;
; 18. Controller Area Network (CAN) Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.      for CAN Module 1
;
;==============================================================================
; 18a. SFR Definitions
;------------------------------------------------------------------------------
;-------------CAN1 Module------------------------------------------------------
         .equiv C1RXF0SIDL, _C1RXF0SID          ; See all SFR descriptions in
         .equiv C1RXF0SIDH, _C1RXF0SID+1        ;  sub-section below
         .equiv C1RXF0EIDHL, _C1RXF0EIDH
         .equiv C1RXF0EIDHH, _C1RXF0EIDH+1
         .equiv C1RXF0EIDLL, _C1RXF0EIDL
         .equiv C1RXF0EIDLH, _C1RXF0EIDL+1
         .equiv C1RXF1SIDL, _C1RXF1SID
         .equiv C1RXF1SIDH, _C1RXF1SID+1
         .equiv C1RXF1EIDHL, _C1RXF1EIDH
         .equiv C1RXF1EIDHH, _C1RXF1EIDH+1
         .equiv C1RXF1EIDLL, _C1RXF1EIDL
         .equiv C1RXF1EIDLH, _C1RXF1EIDL+1
         .equiv C1RXF2SIDL, _C1RXF2SID
         .equiv C1RXF2SIDH, _C1RXF2SID+1
         .equiv C1RXF2EIDHL, _C1RXF2EIDH
         .equiv C1RXF2EIDHH, _C1RXF2EIDH+1
         .equiv C1RXF2EIDLL, _C1RXF2EIDL
         .equiv C1RXF2EIDLH, _C1RXF2EIDL+1
         .equiv C1RXF3SIDL, _C1RXF3SID
         .equiv C1RXF3SIDH, _C1RXF3SID+1