.equiv I2CCONH, _I2CCON+1              ;  section 9b
         .equiv I2CSTATL, _I2CSTAT              ; See I2CSTAT description in
         .equiv I2CSTATH, _I2CSTAT+1            ;  section 9b
         .equiv I2CADDL, _I2CADD
         .equiv I2CADDH, _I2CADD+1

;------------------------------------------------------------------------------
; 7b. Bit Position Definitions for some SFRs

;------------------------------------------------------------------------------
;     I2CCON : I2C Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv I2CEN, 0x000F
         .equiv I2CSIDL, 0x000D
         .equiv SCLREL, 0x000C
         .equiv IPMIEN, 0x000B
         .equiv A10M, 0x000A
         .equiv DISSLW, 0x0009
         .equiv SMEN, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv GCEN, 0x0007
         .equiv STREN, 0x0006
         .equiv ACKDT, 0x0005
         .equiv ACKEN, 0x0004
         .equiv RCEN, 0x0003
         .equiv PEN, 0x0002
         .equiv RSEN, 0x0001
         .equiv SEN, 0x0000

;------------------------------------------------------------------------------
;     I2CSTAT : I2C Status Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv ACKSTAT, 0x000F
         .equiv TRSTAT, 0x000E
         .equiv BCL, 0x000A
         .equiv GCSTAT, 0x0009
         .equiv ADD10, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv IWCOL, 0x0007
         .equiv I2COV, 0x0006
         .equiv D_A, 0x0005
         .equiv P, 0x0004
         .equiv S, 0x0003
         .equiv R_W, 0x0002
         .equiv RBF, 0x0001
         .equiv TBF, 0x0000


;==============================================================================
;
; 8. UARTx Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 8a. SFR Definitions
;------------------------------------------------------------------------------
;------------------UART 1 Module-----------------------------------------------
         .equiv U1MODEL, _U1MODE                ; See UxMODE description in
         .equiv U1MODEH, _U1MODE+1              ;  sub-section below
         .equiv U1STAL, _U1STA                  ; See UxSTA description in
         .equiv U1STAH, _U1STA+1                ;  sub-section below
         .equiv U1TXREGL, _U1TXREG
         .equiv U1TXREGH, _U1TXREG+1
         .equiv U1RXREGL, _U1RXREG
         .equiv U1RXREGH, _U1RXREG+1
         .equiv U1BRGL, _U1BRG
         .equiv U1BRGH, _U1BRG+1

;-------------------UART 2 Module----------------------------------------------
         .equiv U2MODEL, _U2MODE                ; See UxMODE description in
         .equiv U2MODEH, _U2MODE+1              ;  sub-section below
         .equiv U2STAL, _U2STA                  ; See UxSTA description in
         .equiv U2STAH, _U2STA+1                ;  sub-section below
         .equiv U2TXREGL, _U2TXREG
         .equiv U2TXREGH, _U2TXREG+1
         .equiv U2RXREGL, _U2RXREG
         .equiv U2RXREGH, _U2RXREG+1
         .equiv U2BRGL, _U2BRG
         .equiv U2BRGH, _U2BRG+1

;------------------------------------------------------------------------------
; 8b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     UxMODE : UART x Mode Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv UARTEN, 0x000F
         .equiv USIDL, 0x000D
         .equiv ALTIO, 0x000A


; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv WAKE, 0x0007
         .equiv LPBACK, 0x0006
         .equiv ABAUD, 0x0005
         .equiv PDSEL1, 0x0002
         .equiv PDSEL0, 0x0001
         .equiv STSEL, 0x0000

;------------------------------------------------------------------------------
;     UxSTA : UART x Status and Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv UTXISEL, 0x000F
         .equiv UTXBRK, 0x000B
         .equiv UTXEN, 0x000A
         .equiv UTXBF, 0x0009
         .equiv TRMT, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv URXISEL1, 0x0007
         .equiv URXISEL0, 0x0006
         .equiv ADDEN, 0x0005
         .equiv RIDLE, 0x0004
         .equiv PERR, 0x0003
         .equiv FERR, 0x0002
         .equiv OERR, 0x0001
         .equiv URXDA, 0x0000


;==============================================================================
;
; 9. Serial Peripheral Interface Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.      (SPIx)
;==============================================================================
; 9a. SFR Definitions
;------------------------------------------------------------------------------
;------------------SPI 1 Module------------------------------------------------
         .equiv SPI1STATL, _SPI1STAT    ; See SPIxSTAT description in
         .equiv SPI1STATH, _SPI1STAT+1  ;  sub-section below
         .equiv SPI1CONL, _SPI1CON      ; See SPIxCON description in
         .equiv SPI1CONH, _SPI1CON+1    ;  sub-section below
         .equiv SPI1BUFL, _SPI1BUF
         .equiv SPI1BUFH, _SPI1BUF+1

;------------------SPI 2 Module------------------------------------------------
         .equiv SPI2STATL, _SPI2STAT    ; See SPIxSTAT description in
         .equiv SPI2STATH, _SPI2STAT+1  ;  sub-section below
         .equiv SPI2CONL, _SPI2CON      ; See SPIxCON description in
         .equiv SPI2CONH, _SPI2CON+1    ;  sub-section below
         .equiv SPI2BUFL, _SPI2BUF
         .equiv SPI2BUFH, _SPI2BUF+1

;------------------------------------------------------------------------------
; 9b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     SPIxSTAT : SPI x Status register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SPIEN, 0x000F
         .equiv SPISIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv SPIROV, 0x0006
         .equiv SPITBF, 0x0001
         .equiv SPIRBF, 0x0000


;------------------------------------------------------------------------------
;     SPIxCON : SPI x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv FRMEN, 0x000E
         .equiv SPIFSD, 0x000D
         .equiv DISSDO, 0x000B
         .equiv MODE16, 0x000A
         .equiv SMP, 0x0009
         .equiv CKE, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv SSEN, 0x0007
         .equiv CKP, 0x0006
         .equiv MSTEN, 0x0005
         .equiv SPRE2, 0x0004
         .equiv SPRE1, 0x0003
         .equiv SPRE0, 0x0002
         .equiv PPRE1, 0x0001
         .equiv PPRE0, 0x0000


;==============================================================================
;
; 10. Codec/Data Converter Interface Module SFRs and Associated Bits Definition
;      (DCI)
;==============================================================================
;------------------------------------------------------------------------------
;     DCICON1 : Data Converter/Codec Interface Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv DCIEN, 0x000F
         .equiv DCISIDL, 0x000D
         .equiv DLOOP, 0x000B
         .equiv CSCKD, 0x000A
         .equiv CSCKE, 0x0009
         .equiv COFSD, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv UNFM, 0x0007
         .equiv CSDOM, 0x0006
         .equiv DJST, 0x0005
         .equiv COFSM1, 0x0001
         .equiv COFSM0, 0x0000

;------------------------------------------------------------------------------
;     DCICON2 : Data Converter/Codec Interface Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv BLEN1, 0x000B
         .equiv BLEN0, 0x000A
         .equiv COFSG3, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv COFSG2, 0x0007
         .equiv COFSG1, 0x0006
         .equiv COFSG0, 0x0005
         .equiv WS3, 0x0003
         .equiv WS2, 0x0002
         .equiv WS1, 0x0001
         .equiv WS0, 0x0000

;------------------------------------------------------------------------------
;     DCICON3 : Data Converter/Codec Interface Control Register 3
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv BCG11, 0x000B
         .equiv BCG10, 0x000A
         .equiv BCG9, 0x0009
         .equiv BCG8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv BCG7, 0x0007
         .equiv BCG6, 0x0006
         .equiv BCG5, 0x0005
         .equiv BCG4, 0x0004
         .equiv BCG3, 0x0003
         .equiv BCG2, 0x0002
         .equiv BCG1, 0x0001
         .equiv BCG0, 0x0000

;------------------------------------------------------------------------------
;     DCISTAT : Data Converter/Codec Interface Status Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SLOT3, 0x000B
         .equiv SLOT2, 0x000A
         .equiv SLOT1, 0x0009
         .equiv SLOT0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv ROV, 0x0003
         .equiv RFUL, 0x0002
         .equiv TUNF, 0x0001
         .equiv TMPTY, 0x0000

;------------------------------------------------------------------------------
;     TSCON : Transmit Slot Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv TSE15, 0x000F
         .equiv TSE14, 0x000E
         .equiv TSE13, 0x000D
         .equiv TSE12, 0x000C
         .equiv TSE11, 0x000B
         .equiv TSE10, 0x000A
         .equiv TSE9, 0x0009
         .equiv TSE8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TSE7, 0x0007
         .equiv TSE6, 0x0006
         .equiv TSE5, 0x0005
         .equiv TSE4, 0x0004
         .equiv TSE3, 0x0003
         .equiv TSE2, 0x0002
         .equiv TSE1, 0x0001
         .equiv TSE0, 0x0000

;------------------------------------------------------------------------------
;     RSCON : Receive Slot Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv RSE15, 0x000F
         .equiv RSE14, 0x000E
         .equiv RSE13, 0x000D
         .equiv RSE12, 0x000C
         .equiv RSE11, 0x000B
         .equiv RSE10, 0x000A
         .equiv RSE9, 0x0009
         .equiv RSE8, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv RSE7, 0x0007
         .equiv RSE6, 0x0006
         .equiv RSE5, 0x0005
         .equiv RSE4, 0x0004
         .equiv RSE3, 0x0003
         .equiv RSE2, 0x0002
         .equiv RSE1, 0x0001
         .equiv RSE0, 0x0000


;==============================================================================
;
; 11.  A/D Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 11a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv ADCBUF0L, _ADCBUF0
         .equiv ADCBUF0H, _ADCBUF0+1
         .equiv ADCBUF1L, _ADCBUF1
         .equiv ADCBUF1H, _ADCBUF1+1
         .equiv ADCBUF2L, _ADCBUF2
         .equiv ADCBUF2H, _ADCBUF2+1
         .equiv ADCBUF3L, _ADCBUF3
         .equiv ADCBUF3H, _ADCBUF3+1