`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:26:15 01/19/2006 
// Design Name: 
// Module Name:    acc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module acc(
			input clk,
			input reset,
			input intr,
			input code,
			input [7:0]data,
			output reg[31:0]accOut
			);

reg [31:0]acc;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		accOut = 0;
		acc = 0;
	end
	else
	begin
		if(intr)
		begin
			accOut = acc;
			acc = 0;
		end
		else
		begin
		if(code)
			acc = acc + {data[7]?24'hFFFFFF:24'h0,data};
		else
			acc = acc - {data[7]?24'hFFFFFF:24'h0,data};
		end
	end
end
 
endmodule