//////////////////////////////////////////////////////////////////////////////////
// Company: BIT-RRL
// Engineer: Xu Guihang
// 
// Create Date:    20:59:59 05/04/2006 
// Design Name: 
// Module Name:    Acc_2us 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module acc_2us(
			//Global signals
			input clk,
			input reset,
			//Input Data and code
			input [7:0]data,
			input code,
			//Input synchronous signal,CLR
			input clr,
			//Accumulation output
			output reg [14:0]res
				);
reg [14:0]acc;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		acc = 0;
		res = 0;
	end
	else
	begin
		if(clr)//If clr is valid,the accumulated result gives out and clear the acc regs
		begin
			res = acc;
			acc = 0;
		end
		else
		begin
		if(code)
			acc = acc + {data[7]?7'h7F:7'h0,data};
		else
			acc = acc - {data[7]?7'h7F:7'h0,data};
		end
	end
end
endmodule