//////////////////////////////////////////////////////////////////////////////////
// Company: BIT-RRL
// Engineer: Xu Guihang
// 
// Create Date:    20:59:59 05/04/2006 
// Design Name: 
// Module Name:    Acc_2ms 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module acc_2ms(
			//Global signals
			input clk,
			input reset,
			//Input Data and code
			input [31:0]data,
			input enable,
			//Input synchronous signal,CLR
			input clr,
			//Accumulation output
			output reg [31:0]res
				);
reg [35:0]acc;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		acc = 0;
		res = 0;
	end
	else
	begin
		if(clr)//If clk is valid,the accumulated result gives out and clear the acc regs
		begin
			res = acc[35:4];
			acc = 0;
		end
		else
		begin
		if(enable)
			acc = acc + {data[31]?10'h3FF:10'h0,data};
		end
	end
end
endmodule