`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:59:59 01/18/2006 
// Design Name: 
// Module Name:    CodeGen 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CACodeGen(
				//global signal 
				input clk,
				input reset,
				//control words
				input [31:0]phase_cw,	//-2^32 to 2^31-1 represent -1/4 chip to 1/4 chip
				input [31:0]freq_cw,	// To efine the half-chip rate,with the unit fs/2^32
				input [10:0]chip_cw,	//the unit is 1/2 chip
				//code output
				output reg e_code,	//early code
				output reg p_code,	//prompt code
				output reg l_code,	//late code
				//CA code write and read
				input [31:0]data_in,
				output [31:0]data_out,
				input [4:0]wr_addr,
				input code_tab_wr,
				//clr output
				output reg clr,				//Code period synchronous signal, clr is 1 at the last tick of a C/A code period,which is used to time the accumulator
				//cycles count
				output reg [11:0]cycles,	//to remember code cycles
				output [9:0]chips,
				output reg [31:0]phase,//Phase accumulated result
				output reg [18:0]Z_cnt,
				input [11:0]cyc_cw,
				input [18:0]zcnt_cw			
				);
reg chip_sync;		//Chip period synchronous signal. chip_sync is 1 at the last tick of the half-chip 
reg [31:0]phase_add;//the value will be added to the phase
reg [12:0]addr_cnt;	//half chip count
wire [10:0]addr;		//the adress of the code table
reg carry;			//remember the carry bit of phase accumulator, used to generate chip_sync
reg go_back;		//when the phase is going back and the amount is big enough to draw back one half-chip, the go_back sihnal is valid

//Phase accumulate
reg [31:0]acc;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		acc = 0;
		go_back = 0;
		carry = 0;
		phase_add = 0;
		chip_sync = 0;
	end
	else
	begin
		if(clr)
		begin
		// If clr is valid, add phase-control-word and frequncy-control-word to the phase accumulator
			phase_add = phase_cw + freq_cw;
			{carry,acc} = {1'b0,acc} + {1'b0,phase_add};
			
		//If the value added onto the accumulator is negative, and there is no carry, that means we should draw back one half-chip	
			go_back = (carry == 0) && (phase_add[31] == 1);
	
		//The carry is valid to generate chip_sync only when the phase added to the accumulator is positive
			chip_sync = (carry == 1) && (phase_add[31] == 0);//if the control word is minus, no carry generate
		
		end
		else
		begin
		// If clr is not valid,just add frequncy-control-word to the phase accumulator
			go_back = 0;
			{carry,acc} = {1'b0,acc} + {1'b0,freq_cw};
		//The carry is the chip_sync
			chip_sync = carry;
		end 
	end
end

//Mode 2046 counter
wire e_code_noreg;
reg [12:0]cycles_temp;
reg [18:0]Z_cnt_temp;
reg [18:0]Z_cnt_add;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		addr_cnt = 0;
		cycles = 0;
		e_code = 0;
		p_code = 0;
		l_code = 0;
		Z_cnt = 0;
		Z_cnt_temp = 0;
		cycles_temp = 0;
		Z_cnt_add = 0;
	end
	else
	begin	
	//
		if(Z_cnt_temp > 403199)
		begin
			Z_cnt = Z_cnt_temp - 403200;
			Z_cnt_temp = Z_cnt;
		end
		else
		begin
			Z_cnt = Z_cnt_temp;
		end	
		Z_cnt_temp = Z_cnt_temp + Z_cnt_add;

	//chip_sync means to go forward
		if(clr)
		begin
			addr_cnt = addr_cnt + chip_cw;
			cycles_temp = cycles + cyc_cw;
			if(cycles_temp > 1499)
			begin
				cycles = cycles_temp - 1500;
				Z_cnt_add = zcnt_cw + 1;
			end
			else
			begin
				cycles = cycles_temp;
				Z_cnt_add = zcnt_cw;
			end
		end
		else
		begin
			if(chip_sync == 1)
			begin
				if(addr_cnt >= 2045)
				begin
					addr_cnt = addr_cnt - 2045;
					if(cycles == 1499)
					begin
						cycles = 0;
						Z_cnt_add = 1;			
					end
					else
					begin
						cycles = cycles + 1;
						Z_cnt_add = 0;
					end
				end
				else
				begin
					addr_cnt = addr_cnt + 1;
					Z_cnt_add = 0;
				end
				l_code = p_code;
				p_code = e_code;
				e_code = e_code_noreg;
			end
			else
			begin
				Z_cnt_add = 0;
			end
	
		//go_back menas to go back
			if(go_back == 1)
			begin
				if(addr_cnt == 0)
				begin
					addr_cnt = 2045;
				end
				else
				begin
					addr_cnt = addr_cnt - 1;
				end
			end
		end
	end
end

//Add the chip control word
//always@(posedge clk or negedge reset)
//begin
//	if(~reset)
//	begin
//		addr = 0;
//	end
//	else
//	begin
//		addr = {24'b0,addr_cnt} + {24'b0,chip_cw};
//
//		//addr mod 2046
//		if(addr > 2045)
//		begin
//			addr = addr - 2046;
//		end
//	end
//end
assign addr = addr_cnt;
//Generate the Code Period pulse
reg last_add;
reg [15:0] cnt;//A countor to avoid "Draw Back Loop"
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		last_add = 0;
		cnt = 0;
		clr = 0;
	end
	else
	begin
		clr = (cnt > 10000) && (last_add == 1 && addr[10] == 0);


		if(last_add == 1 && addr[10] == 0) 
		begin
			cnt = 0;
		end
		else
		begin
			cnt = cnt + 1;
		end
		last_add = addr[10];
	end
end

wire [31:0]dout;
dp_ca_code_table code_tab1(
						.addra(addr[10:6]),
						.douta(dout),
						.addrb(wr_addr[4:0]),
						.clka(clk),
						.clkb(clk),
						.dinb(data_in),
						.doutb(data_out),
						.web(code_tab_wr)
				);
assign chips = addr[10:1];
//assign phase = {addr[0],acc[31:1]};
//reg Acc 3 times and addr 2 times to make synchronous
reg [31:0]acc_reg1,acc_reg2;
always@(posedge clk or negedge reset)
begin
	if(~reset)
	begin
		acc_reg1 = 0;
		acc_reg2 = 0;
	end
	else
	begin
		phase = acc_reg2;
		acc_reg2 = {addr[0],acc_reg1[31:1]};
		acc_reg1 = acc;		
	end
end
assign e_code_noreg = dout[addr[5:1]];
endmodule