LIBRARY  ieee; 
USE  ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;


ENTITY  rx_mii_interface  IS
PORT
( --mii 
	rx_dvr       	:IN  STD_LOGIC;
 	rx_dvl 		:IN  STD_LOGIC;
 	rv_err        	:IN  STD_LOGIC;
 	rv_erl        		 :IN  STD_LOGIC;
 	rxcr               	:IN  STD_LOGIC;
 	rxcl               	:IN  STD_LOGIC;
 	rxdr              	:IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
 	rxdl              	:IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
 --fifo
 	rx_fifo_aclr  	:IN  STD_LOGIC;
 	rx_fifo_q            	:OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
 	rx_fifo_rdreq     	:IN  STD_LOGIC;
 	rx_fifo_rdclk		:IN STD_LOGIC;
 	rx_fifo_rdempty 	:OUT STD_LOGIC;
 --TEST SIGNAL
--	data		: out STD_LOGIC_VECTOR (7 DOWNTO 0);
--	wrreq		: out STD_LOGIC ;
--	wrclk		: out STD_LOGIC ;
--	aclr		: out STD_LOGIC  := '0';
--	wrfull		: OUT STD_LOGIC;
 --globe
 	frame_valid  	:OUT 	STD_LOGIC;
 	remote_local_sel      :IN  STD_LOGIC;       --1:re 0:lo
 	reset             	:IN  STD_LOGIC
);
END rx_mii_interface;

ARCHITECTURE rtl OF  rx_mii_interface  IS

CONSTANT set_type       :STD_LOGIC_VECTOR (3 DOWNTO 0) :="1011";
CONSTANT com_type     :STD_LOGIC_VECTOR (3 DOWNTO 0) :="1000";
SIGNAL counter               :INTEGER RANGE 0 TO 31;
SIGNAL frame_type         :STD_LOGIC;
 
COMPONENT fifo32x8 
PORT
(		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		rdclk		: IN STD_LOGIC ;
		wrclk		: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdempty		: OUT STD_LOGIC ;
		wrfull		: OUT STD_LOGIC 
);
END COMPONENT;
SIGNAL clk		:STD_LOGIC;
SIGNAL wrreq_sig  		:STD_LOGIC;
--SIGNAL rdclock_sig 	:STD_LOGIC;
SIGNAL wrclock_sig 	:STD_LOGIC;
SIGNAL aclr_sig 		:STD_LOGIC;
SIGNAL fifo_aclr		:STD_LOGIC;
SIGNAL wrfull_sig 		:STD_LOGIC;
SIGNAL rx_dv 		:STD_LOGIC;
SIGNAL rv_er		:STD_LOGIC;
SIGNAL rxd 		:STD_LOGIC_VECTOR (3 DOWNTO 0);
--SIGNAL type_bype :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL receive_byte 	:STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_sig 		:STD_LOGIC_VECTOR (7 DOWNTO 0);

TYPE STATE_TYPE  IS(
idle,fifo_re_aclr,re_preamble,frame_type_low,frame_type_high,
first_data_low,first_data_high,valid_data_low,valid_data_high,
last_low,last_high,over,over_delay);
SIGNAL state  : STATE_TYPE;

BEGIN
--	data	<=data_sig;
--	wrreq	<=wrreq_sig;
--	wrclk	<=wrclock_sig;
--	aclr	<=fifo_aclr;
--	wrfull	<=wrfull_sig;

fifo_aclr<=aclr_sig OR rx_fifo_aclr;
fifo32x8_inst : fifo32x8 PORT MAP(
		data	 => data_sig,
		wrreq	 => wrreq_sig,                                            
		rdreq	 => rx_fifo_rdreq,
		rdclk	 => rx_fifo_rdclk,
		wrclk	 => wrclock_sig,
		aclr	 => fifo_aclr,
		q	 => rx_fifo_q,
		rdempty	 => rx_fifo_rdempty,
		wrfull	 => wrfull_sig
	);

PROCESS(rxcl,rxcr,rxdl,rx_dvl,rv_erl,rxdr,rx_dvr,rv_err,remote_local_sel)
BEGIN
IF remote_local_sel='0'   THEN
	wrclock_sig<= NOT rxcl;
	clk  <= rxcl;
	rxd <=rxdl;
	rx_dv <=rx_dvl;
	rv_er <=rv_erl;
ELSE  
	wrclock_sig<= NOT rxcr;
	clk  <= rxcr;
	rxd <=rxdr;
	rx_dv <=rx_dvr;
	rv_er <=rv_err;
END IF;
END PROCESS;
data_sig <=receive_byte;
PROCESS(reset,clk)
BEGIN
IF reset='1'  THEN   
    aclr_sig <='1';
    state<=idle;
	counter<=0;
	receive_byte<="00000000";
	wrreq_sig<='0';
	frame_valid<='0';
	frame_type<='0';
ELSIF  rising_edge(clk)  THEN
CASE state  IS
	WHEN idle  =>
		frame_type<='0';
		aclr_sig <='0';
		wrreq_sig<='0';
		counter<=0;
    		IF rx_dv='1' THEN
    		 state <=fifo_re_aclr;
     		END IF;

	WHEN  fifo_re_aclr  =>
		IF rxd="1010"   THEN   
     			state <=re_preamble;
     		END IF;
     		 aclr_sig <='1';

	WHEN re_preamble  =>                          
		 aclr_sig <='0';
     		IF rxd="1010"   THEN   
     			state <=re_preamble;
    		ELSIF rxd="1011" THEN
    			state <=frame_type_low;
     		ELSE state <=idle;
     		END IF;
	WHEN frame_type_low   =>
	                IF rv_er='1'  THEN
	                                 state <=idle;
	                 ELSE
	                          	 state <=frame_type_high;
      		END IF;
		receive_byte(3 DOWNTO 0) <=rxd;
          		
	WHEN frame_type_high =>
		wrreq_sig<='1';
		receive_byte(7 DOWNTO 4) <=rxd;
		 IF rv_er='1'  THEN
	                                 state <=idle;
	                ELSE
     			IF receive_byte(3 DOWNTO 0)=set_type THEN
     				frame_type<='0';
     				state <=first_data_low;
      			ELSIF receive_byte(3 DOWNTO 0)=com_type THEN
      				frame_type<='1';
      				state <=first_data_low;
      			ELSE 
      				state <=idle;
       			END IF;
     		END IF;
	WHEN first_data_low =>
	                           
		wrreq_sig<='0';
     		receive_byte(3 DOWNTO 0) <=rxd;
     		IF  counter=7 THEN
     			state <=valid_data_low;
     		ELSE 
     			state <=first_data_high;
     		END IF;

	WHEN first_data_high =>
	                IF rv_er='1'  THEN
	                                 state <=idle;
	                ELSE
	               		  state <=first_data_low; 
	                END IF;
		wrreq_sig<='1';
     		receive_byte(7 DOWNTO 4) <=rxd;     
     		counter <=counter+1;
	
	WHEN valid_data_low =>
	                  counter <=counter+1;         
		wrreq_sig<='1';
     		receive_byte(7 DOWNTO 4) <=rxd;
     		 IF rv_er='1'  THEN
	                                 state <=idle;
	                 ELSIF frame_type='0' THEN
     			IF counter =14 THEN
    				state <=last_low;
    			ELSE
    				 state <=valid_data_high; 
     			END IF;     
     		ELSE 
     			IF counter =8 THEN
    				 frame_valid <='1';
    			 	state <=over;
    			ELSe	state <=valid_data_high; 
    			
     			END IF;     
     		END IF;

	WHEN valid_data_high =>
	        IF rv_er='1'  THEN
	                state <=idle;
	        ELSIF	receive_byte(3 DOWNTO 0) =receive_byte(7 DOWNTO 4) THEN	
    			state <=valid_data_low; 
    		ELSE
    			state <=idle;
	               	END IF;
		wrreq_sig<='0';
     		receive_byte(3 DOWNTO 0) <=rxd;     
     		
		
	WHEN last_low =>
	                           
		wrreq_sig<='0';
     		receive_byte(3 DOWNTO 0) <=rxd;
     		 IF rv_er='1'  THEN
	                                 state <=idle;
	                 ELSIF  counter =23 THEN
    				 frame_valid <='1';
    			 	state <=over;
	                 ELSE 			
    			state <=last_high; 
    		END IF;       
     		

	WHEN last_high =>
	                IF rv_er='1'  THEN
	                                 state <=idle;
	                ELSE
	               		  state <=last_low; 
	                END IF;
		wrreq_sig<='1';
     		receive_byte(7 DOWNTO 4) <=rxd;     
     		counter <=counter+1;	

	WHEN over  =>
		wrreq_sig<='0';
          		state <=over_delay;

     	WHEN over_delay =>
     		frame_valid <='0';
     		state <=idle;

     	WHEN OTHERS=>
     		state <=idle;
END CASE;
END IF;
END PROCESS;

END rtl;