LIBRARY ieee;
USE ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;


ENTITY mii_tx_model1 IS
	PORT
	(
    --MII INTERFACE
		--MII TX PORT
		tx_clk			:IN STD_LOGIC;
		mii_tx_en			:OUT STD_LOGIC;
		mii_tx_data		:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	--FIFO INTERFACE
		fifo_data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		fifo_wrreq		: IN STD_LOGIC ;
		fifo_wrclock		: IN STD_LOGIC ;
		fifo_aclr			: IN STD_LOGIC  := '0';
		fifo_wrfull		: OUT STD_LOGIC ;

	--fifo for test
-- tfifo_q		: out STD_LOGIC_VECTOR (7 DOWNTO 0);
-- tfifo_rdempty	:out  STD_LOGIC;
-- tfifo_rdreq	: out STD_LOGIC;
-- tfifo_rdclock	:out STD_LOGIC;

	--GLOBAL 
		reset			:IN STD_LOGIC
	);
END mii_tx_model1;

ARCHITECTURE rtl OF mii_tx_model1 IS
	COMPONENT small_counter
	PORT (
			aclr	: IN STD_LOGIC ;
			clock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	END COMPONENT;
	SIGNAL aclr  : STD_LOGIC ;
	SIGNAL clock : STD_LOGIC ;
	SIGNAL q	 : STD_LOGIC_VECTOR (3 DOWNTO 0);


	COMPONENT dc_fifo_256x8 	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		rdclk		: IN STD_LOGIC ;
		wrclk		: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdempty		: OUT STD_LOGIC ;
		wrfull		: OUT STD_LOGIC 
	);
	END COMPONENT;
	SIGNAL fifo_q		: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL fifo_rdempty	: STD_LOGIC;
	SIGNAL fifo_rdreq	: STD_LOGIC;
	SIGNAL fifo_rdclock	: STD_LOGIC;


	TYPE STATE_TYPE IS (idle,wait_n_clock,tx_nib0,tx_nib1);--,tx_last);
	SIGNAL state: STATE_TYPE;
BEGIN
small_counter_inst : small_counter PORT MAP(
		clock	 => clock,
		aclr	 => aclr,
		q	 => q	);

dc_fifo_256x8_inst : dc_fifo_256x8 PORT MAP(
		data	 => fifo_data,
		wrreq	 => fifo_wrreq,
		rdreq	 => fifo_rdreq,
		rdclk	 => fifo_rdclock,
		wrclk	 => fifo_wrclock,
		aclr	 => fifo_aclr,
		q	 => fifo_q,
		rdempty	 => fifo_rdempty,
		wrfull	 => fifo_wrfull
	);

clock <= tx_clk;
fifo_rdclock <= tx_clk;

--	tfifo_q		<= fifo_q		;
--	tfifo_rdempty	<= fifo_rdempty	;
	--tfifo_rdreq<= fifo_rdreq;
--	tfifo_rdclock<=	 fifo_rdclock	;	

	PROCESS (tx_clk,reset)
		BEGIN
		IF reset = '1' THEN
			state 		<= idle;
			mii_tx_en	<='0';
			fifo_rdreq		<='0';	
			aclr 		<='1';
			mii_tx_data<="0000";
		ELSIF tx_clk'EVENT AND tx_clk = '0' THEN  --falling edge
			CASE state IS
				WHEN idle =>
					mii_tx_en	<='0';
					fifo_rdreq		<='0';		
					IF  fifo_rdempty='0' THEN
						state <=wait_n_clock;
						aclr <='0'; 		--start the small counter
					END IF;

				WHEN wait_n_clock =>
					IF  q="0000" THEN
						state <=tx_nib0;
						fifo_rdreq<='1';
						aclr <='1';            --stop the small counter
					END IF;

				WHEN tx_nib0 =>
						state <=tx_nib1;
						mii_tx_en<='1';
						mii_tx_data<=fifo_q(3 DOWNTO 0);
						fifo_rdreq<='0';
	
				WHEN tx_nib1 =>
						fifo_rdreq<='1';
						mii_tx_data<=fifo_q(7 DOWNTO 4);
					IF  fifo_rdempty='1' THEN
						state <=idle;--tx_last;
						fifo_rdreq<='0';
					ELSE state <= tx_nib0;
					END IF;

			--	WHEN tx_last =>
				--		state <=idle;
						--mii_tx_en<='0';
					--	mii_tx_data<=fifo_q(3 DOWNTO 0);
						--rd_req<='0';


				WHEN OTHERS =>	
						state <= idle;
			END CASE;
		END IF;
	END PROCESS;




END rtl;