Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.53 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.53 s | Elapsed : 0.00 / 1.00 s --> Reading design: Hand_Shake.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "Hand_Shake.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "Hand_Shake"Output Format                      : NGCTarget Device                      : xc3s100e-5-vq100---- Source OptionsTop Module Name                    : Hand_ShakeAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : Hand_Shake.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd" in Library work.Architecture behavioral of Entity c_muller_gate is up to date.Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd" in Library work.Architecture behavioral of Entity inverter is up to date.Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd" in Library work.Architecture structural of Entity hand_shake is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <Hand_Shake> (Architecture <structural>).Entity <Hand_Shake> analyzed. Unit <Hand_Shake> generated.Analyzing Entity <C_MULLER_GATE> (Architecture <behavioral>).Entity <C_MULLER_GATE> analyzed. Unit <C_MULLER_GATE> generated.Analyzing Entity <Inverter> (Architecture <behavioral>).Entity <Inverter> analyzed. Unit <Inverter> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <Inverter>.    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd".Unit <Inverter> synthesized.Synthesizing Unit <C_MULLER_GATE>.    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd".WARNING:Xst:737 - Found 1-bit latch for signal <Output>.INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.Unit <C_MULLER_GATE> synthesized.Synthesizing Unit <Hand_Shake>.    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd".Unit <Hand_Shake> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Latches                                              : 2 1-bit latch                                           : 2==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Latches                                              : 2 1-bit latch                                           : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx8.1.Optimizing unit <Hand_Shake> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block Hand_Shake, actual ratio is 0.Latch C_2/Output has been replicated 1 time(s) to handle iob=true attribute.Latch C_1/Output has been replicated 2 time(s) to handle iob=true attribute.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : Hand_Shake.ngrTop Level Output File Name         : Hand_ShakeOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 6Cell Usage :# BELS                             : 4#      LUT3                        : 4# FlipFlops/Latches                : 5#      LD                          : 5# IO Buffers                       : 6#      IBUF                        : 3#      OBUF                        : 3=========================================================================Device utilization summary:---------------------------Selected Device : 3s100evq100-5  Number of Slices:                       3  out of    960     0%   Number of Slice Flip Flops:             2  out of   1920     0%   Number of 4 input LUTs:                 4  out of   1920     0%   Number of bonded IOBs:                  6  out of     66     9%      IOB Flip Flops: 3=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+C_2/_n0009(C_2/_n00091:O)          | NONE(*)(C_2/Output_1)  | 2     |C_1/_n0009(C_1/_n00091:O)          | NONE(*)(C_1/Output_2)  | 3     |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: 2.917ns   Maximum output required time after clock: 4.179ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'C_2/_n0009'  Total number of paths / destination ports: 4 / 2-------------------------------------------------------------------------Offset:              2.883ns (Levels of Logic = 2)  Source:            Rec_Ack (PAD)  Destination:       C_2/Output (LATCH)  Destination Clock: C_2/_n0009 falling  Data Path: Rec_Ack to C_2/Output                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             2   1.106   0.897  Rec_Ack_IBUF (Rec_Ack_IBUF)     LUT3:I0->O            2   0.612   0.000  C_2/_n00011 (C_2/_n0001)     LD:D                      0.268          C_2/Output    ----------------------------------------    Total                      2.883ns (1.986ns logic, 0.897ns route)                                       (68.9% logic, 31.1% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'C_1/_n0009'  Total number of paths / destination ports: 6 / 3-------------------------------------------------------------------------Offset:              2.917ns (Levels of Logic = 2)  Source:            Reset (PAD)  Destination:       C_1/Output (LATCH)  Destination Clock: C_1/_n0009 falling  Data Path: Reset to C_1/Output                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             4   1.106   0.931  Reset_IBUF (Reset_IBUF)     LUT3:I0->O            3   0.612   0.000  C_1/_n00011 (C_1/_n0001)     LD:D                      0.268          C_1/Output    ----------------------------------------    Total                      2.917ns (1.986ns logic, 0.931ns route)                                       (68.1% logic, 31.9% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'C_2/_n0009'  Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Offset:              4.179ns (Levels of Logic = 1)  Source:            C_2/Output_1 (LATCH)  Destination:       Start (PAD)  Source Clock:      C_2/_n0009 falling  Data Path: C_2/Output_1 to Start                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     LD:G->Q               1   0.588   0.681  C_2/Output_1 (C_2/Output_1)     OBUF:I->O                 2.910          Start_OBUF (Start)    ----------------------------------------    Total                      4.179ns (3.498ns logic, 0.681ns route)                                       (83.7% logic, 16.3% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'C_1/_n0009'  Total number of paths / destination ports: 2 / 2-------------------------------------------------------------------------Offset:              4.179ns (Levels of Logic = 1)  Source:            C_1/Output_1 (LATCH)  Destination:       Send_Ack (PAD)  Source Clock:      C_1/_n0009 falling  Data Path: C_1/Output_1 to Send_Ack                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     LD:G->Q               1   0.588   0.681  C_1/Output_1 (C_1/Output_1)     OBUF:I->O                 2.910          Send_Ack_OBUF (Send_Ack)    ----------------------------------------    Total                      4.179ns (3.498ns logic, 0.681ns route)                                       (83.7% logic, 16.3% route)=========================================================================CPU : 33.42 / 34.43 s | Elapsed : 33.00 / 34.00 s --> Total memory usage is 116552 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    1 (   0 filtered)Number of infos    :    2 (   0 filtered)