Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 4.25 s | Elapsed : 0.00 / 4.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 4.25 s | Elapsed : 0.00 / 4.00 s --> Reading design: Full_Adder.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "Full_Adder.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "Full_Adder"Output Format                      : NGCTarget Device                      : xc3s100e-5-vq100---- Source OptionsTop Module Name                    : Full_AdderAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : Full_Adder.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd" in Library work.Architecture behavioral of Entity full_adder is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <Full_Adder> (Architecture <behavioral>).Entity <Full_Adder> analyzed. Unit <Full_Adder> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <Full_Adder>.    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd".    Found 1-bit register for signal <Done>.    Found 1-bit register for signal <Output>.    Found 1-bit register for signal <CarryOut>.    Found 2-bit adder carry in for signal <sum>.    Summary:	inferred   3 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).Unit <Full_Adder> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors                                   : 1 2-bit adder carry in                                  : 1# Registers                                            : 3 1-bit register                                        : 3==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Adders/Subtractors                                   : 1 2-bit adder carry in                                  : 1# Registers                                            : 3 Flip-Flops                                            : 3==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx8.1.Optimizing unit <Full_Adder> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block Full_Adder, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : Full_Adder.ngrTop Level Output File Name         : Full_AdderOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 10Cell Usage :# BELS                             : 4#      LUT2                        : 1#      LUT3                        : 1#      LUT4                        : 1#      VCC                         : 1# FlipFlops/Latches                : 3#      FDC                         : 3# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 9#      IBUF                        : 6#      OBUF                        : 3=========================================================================Device utilization summary:---------------------------Selected Device : 3s100evq100-5  Number of Slices:                       3  out of    960     0%   Number of 4 input LUTs:                 3  out of   1920     0%   Number of bonded IOBs:                 10  out of     66    15%      IOB Flip Flops: 3 Number of GCLKs:                        1  out of     24     4%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+Start                              | BUFGP                  | 3     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: 4.245ns   Maximum output required time after clock: 4.105ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'Start'  Total number of paths / destination ports: 8 / 2-------------------------------------------------------------------------Offset:              4.245ns (Levels of Logic = 3)  Source:            CarryIn (PAD)  Destination:       CarryOut (FF)  Destination Clock: Start rising  Data Path: CarryIn to CarryOut                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             2   1.106   0.897  CarryIn_IBUF (CarryIn_IBUF)     LUT4:I0->O            1   0.612   0.750  Full_Adder_01_xo<1>1 (N4)     LUT2:I1->O            1   0.612   0.000  Full_Adder_01_xo<1>2 (sum<1>)     FDC:D                     0.268          CarryOut    ----------------------------------------    Total                      4.245ns (2.598ns logic, 1.647ns route)                                       (61.2% logic, 38.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Start'  Total number of paths / destination ports: 3 / 3-------------------------------------------------------------------------Offset:              4.105ns (Levels of Logic = 1)  Source:            CarryOut (FF)  Destination:       CarryOut (PAD)  Source Clock:      Start rising  Data Path: CarryOut to CarryOut                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDC:C->Q              1   0.514   0.681  CarryOut (CarryOut_OBUF)     OBUF:I->O                 2.910          CarryOut_OBUF (CarryOut)    ----------------------------------------    Total                      4.105ns (3.424ns logic, 0.681ns route)                                       (83.4% logic, 16.6% route)=========================================================================CPU : 34.69 / 39.57 s | Elapsed : 34.00 / 39.00 s --> Total memory usage is 115528 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)