--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 8.1i
--  \   \         Application : ISE
--  /   /         Filename : TB_Pipeline_Adder.ant
-- /___/   /\     Timestamp : Fri May 19 23:30:47 2006
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: TB_Pipeline_Adder
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY TB_Pipeline_Adder IS
END TB_Pipeline_Adder;

ARCHITECTURE testbench_arch OF TB_Pipeline_Adder IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "C:\Documents and Settings\People\Desktop\VLSIASS2\TB_Pipeline_Adder.ano";

    COMPONENT PipeLine_Adder
        PORT (
            InputA : In std_logic_vector (2 DownTo 0);
            InputB : In std_logic_vector (2 DownTo 0);
            Request : In std_logic;
            Acknowledge : In std_logic;
            Reset : In std_logic;
            Carry_In : In std_logic;
            Done : Out std_logic;
            Output : Out std_logic_vector (3 DownTo 0)
        );
    END COMPONENT;

    SIGNAL InputA : std_logic_vector (2 DownTo 0) := "000";
    SIGNAL InputB : std_logic_vector (2 DownTo 0) := "000";
    SIGNAL Request : std_logic := '0';
    SIGNAL Acknowledge : std_logic := '0';
    SIGNAL Reset : std_logic := '1';
    SIGNAL Carry_In : std_logic := '0';
    SIGNAL Done : std_logic := 'U';
    SIGNAL Output : std_logic_vector (3 DownTo 0) := "UUUU";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    BEGIN
        UUT : PipeLine_Adder
        PORT MAP (
            InputA => InputA,
            InputB => InputB,
            Request => Request,
            Acknowledge => Acknowledge,
            Reset => Reset,
            Carry_In => Carry_In,
            Done => Done,
            Output => Output
        );

        PROCESS    -- Annotation process
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_Done(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", Done, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Done);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_Output(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", Output, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Output);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_Done(0);
            ANNOTATE_Output(0);
            ANNO_LOOP : LOOP
                WAIT for 50 ns;
                TX_TIME := TX_TIME + 50;
                ANNOTATE_Done(TX_TIME);
                ANNOTATE_Output(TX_TIME);
                WAIT for 50 ns;
                TX_TIME := TX_TIME + 50;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  500ns
                WAIT FOR 500 ns;
                Reset <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  2700ns
                WAIT FOR 2200 ns;
                InputA <= "111";
                -- -------------------------------------
                -- -------------  Current Time:  2900ns
                WAIT FOR 200 ns;
                Request <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  5000ns
                WAIT FOR 2100 ns;
                Request <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  6700ns
                WAIT FOR 1700 ns;
                Request <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  7700ns
                WAIT FOR 1000 ns;
                Request <= '1';
                -- -------------------------------------
                WAIT FOR 2300 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;