library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Bit_Pipeline_Adder is    Port ( InputA : in  STD_LOGIC;			  InputB : in STD_LOGIC;           Req : in  STD_LOGIC;           Output : out  STD_LOGIC;           Carry_Out : out  STD_LOGIC;			  Carry_In : in  STD_LOGIC;           Done : out  STD_LOGIC;           RecAck : in  STD_LOGIC;           SendAck : out  STD_LOGIC;			  Reset : in STD_LOGIC);end Bit_Pipeline_Adder;architecture Behavioral of Bit_Pipeline_Adder isCOMPONENT Adder_Register    Port ( Input : in  STD_LOGIC_VECTOR (1 downto 0);           Output : out  STD_LOGIC_VECTOR (1 downto 0);			  Reset : in STD_LOGIC;           Enable : in  STD_LOGIC);End Component;COMPONENT Full_Adder    Port ( inA : in STD_LOGIC_VECTOR (1 downto 0);           inB : in STD_LOGIC_VECTOR (1 downto 0);           Start : in  STD_LOGIC;           Done : out  STD_LOGIC;			  Reset : in STD_LOGIC;           Output : out  STD_LOGIC;			  CarryIn : in STD_LOGIC;			  CarryOut : out STD_LOGIC);End Component;COMPONENT Hand_Shake    Port ( Req : in  STD_LOGIC;           Send_Ack : out  STD_LOGIC;           En : out  STD_LOGIC;           Start : out  STD_LOGIC;			  Reset : in STD_LOGIC;           Rec_Ack : in  STD_LOGIC);End Component;signal Reg_Out : STD_LOGIC_VECTOR (1 downto 0);signal HS_Start : STD_LOGIC;signal HS_En : STD_LOGIC;beginFA_1: Full_Adder	PORT MAP (inA(0) => Reg_Out(1),				 inA(1) => '0',				 inB(0) => Reg_Out(0),				 inB(1) => '0',				 Start => HS_Start,				 Done => Done,				 Reset => Reset,				 Output => Output,				 CarryIn => Carry_In,				 CarryOut => Carry_Out);				 R_1: Adder_Register	PORT MAP (Input(1) => InputB,				 Input(0) => InputA,				 Reset => Reset,				 Output => Reg_Out,				 Enable => HS_En);				 HS_1: Hand_Shake	PORT MAP (Req => Req,				 Send_Ack => SendAck,				 En => HS_En,				 Start => HS_Start,				 Reset => Reset,				 Rec_Ack => RecAck);end Behavioral;