library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Two_Delays is    Port ( Input : in  STD_LOGIC;           Output : out  STD_LOGIC);end Two_Delays;architecture Behavioral of Two_Delays isCOMPONENT Delay_Element		Port ( Input : in STD_LOGIC;				Output : out STD_LOGIC);End COMPONENT;signal Delay_1_Out : STD_LOGIC;beginDelay1: Delay_Element	Port Map( Input => Input,				Output => Delay_1_Out);Delay2: Delay_Element	Port Map( Input => Delay_1_Out,				Output => Output);end Behavioral;