?? tb_bit_pipeline_adder.tbw
字號:
version 3
C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd
Bit_Pipeline_Adder
VHDL
VHDL
TB_Bit_Pipeline_Adder.xwv
Comb
50000000
50000000
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Carry_Out_DIFF
Done_DIFF
Output_DIFF
SendAck_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
Carry_In
Carry_Out
SIGNAL_ORDER_END
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