source {C:/Xilinx8.1/data/projnav/scripts/VsimStopServer.tcl}
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vcom -explicit  -93 Inverter.vhd
vcom -explicit  -93 C_MULLER_GATE.vhd
vcom -explicit  -93 Register.vhd
vcom -explicit  -93 Hand_Shake.vhd
vcom -explicit  -93 Full_Adder.vhd
vcom -explicit  -93 Delay_Element.vhd
vcom -explicit  -93 Two_Delays.vhd
vcom -explicit  -93 1_Bit_Pipeline_Adder.vhd
vcom -explicit  -93 PipeLine_Adder.vhd
vcom -explicit  -93 "TB_Pipeline_Adder.ant"
vsim -t 1ps   -lib work TB_Pipeline_Adder
run -all
quit -force