library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Delay_Element is    Port ( Input : in  STD_LOGIC;           Output : out  STD_LOGIC);end Delay_Element;architecture Behavioral of Delay_Element isbeginOutput <= Input after 10 ns;end Behavioral;