?? tb_bit_pipeline_adder.vhw
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 8.1i
-- \ \ Application : ISE
-- / / Filename : TB_Bit_Pipeline_Adder.vhw
-- /___/ /\ Timestamp : Fri May 19 23:16:52 2006
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: TB_Bit_Pipeline_Adder
--Device: Xilinx
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY TB_Bit_Pipeline_Adder IS
END TB_Bit_Pipeline_Adder;
ARCHITECTURE testbench_arch OF TB_Bit_Pipeline_Adder IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT Bit_Pipeline_Adder
PORT (
InputA : In std_logic;
InputB : In std_logic;
Req : In std_logic;
Output : Out std_logic;
Carry_Out : Out std_logic;
Carry_In : In std_logic;
Done : Out std_logic;
RecAck : In std_logic;
SendAck : Out std_logic;
Reset : In std_logic
);
END COMPONENT;
SIGNAL InputA : std_logic := '0';
SIGNAL InputB : std_logic := '0';
SIGNAL Req : std_logic := '0';
SIGNAL Output : std_logic := 'U';
SIGNAL Carry_Out : std_logic := 'U';
SIGNAL Carry_In : std_logic := '0';
SIGNAL Done : std_logic := 'U';
SIGNAL RecAck : std_logic := '0';
SIGNAL SendAck : std_logic := 'U';
SIGNAL Reset : std_logic := '1';
SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;
BEGIN
UUT : Bit_Pipeline_Adder
PORT MAP (
InputA => InputA,
InputB => InputB,
Req => Req,
Output => Output,
Carry_Out => Carry_Out,
Carry_In => Carry_In,
Done => Done,
RecAck => RecAck,
SendAck => SendAck,
Reset => Reset
);
PROCESS
PROCEDURE CHECK_Carry_Out(
next_Carry_Out : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (Carry_Out /= next_Carry_Out) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns Carry_Out="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Carry_Out);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Carry_Out);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Done(
next_Done : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (Done /= next_Done) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns Done="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Done);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Done);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Output(
next_Output : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (Output /= next_Output) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns Output="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Output);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Output);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_SendAck(
next_SendAck : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (SendAck /= next_SendAck) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns SendAck="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, SendAck);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_SendAck);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 50ns
WAIT FOR 50 ns;
CHECK_Done('0', 50);
CHECK_Output('0', 50);
CHECK_SendAck('0', 50);
CHECK_Carry_Out('0', 50);
-- -------------------------------------
-- ------------- Current Time: 100ns
WAIT FOR 50 ns;
Reset <= '0';
-- -------------------------------------
-- ------------- Current Time: 300ns
WAIT FOR 200 ns;
InputA <= '1';
Req <= '1';
-- -------------------------------------
-- ------------- Current Time: 350ns
WAIT FOR 50 ns;
CHECK_Done('1', 350);
CHECK_Output('1', 350);
CHECK_SendAck('1', 350);
WAIT FOR 650 ns;
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
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