?? tb_full_adder.vhw
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 8.1i
-- \ \ Application : ISE
-- / / Filename : TB_Full_Adder.vhw
-- /___/ /\ Timestamp : Fri May 19 19:59:31 2006
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: TB_Full_Adder
--Device: Xilinx
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY TB_Full_Adder IS
END TB_Full_Adder;
ARCHITECTURE testbench_arch OF TB_Full_Adder IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT Full_Adder
PORT (
inA : In std_logic_vector (1 DownTo 0);
inB : In std_logic_vector (1 DownTo 0);
Start : In std_logic;
Done : Out std_logic;
Reset : In std_logic;
Output : Out std_logic;
CarryIn : In std_logic;
CarryOut : Out std_logic
);
END COMPONENT;
SIGNAL inA : std_logic_vector (1 DownTo 0) := "00";
SIGNAL inB : std_logic_vector (1 DownTo 0) := "00";
SIGNAL Start : std_logic := '0';
SIGNAL Done : std_logic := 'U';
SIGNAL Reset : std_logic := '1';
SIGNAL Output : std_logic := 'U';
SIGNAL CarryIn : std_logic := '0';
SIGNAL CarryOut : std_logic := 'U';
SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;
BEGIN
UUT : Full_Adder
PORT MAP (
inA => inA,
inB => inB,
Start => Start,
Done => Done,
Reset => Reset,
Output => Output,
CarryIn => CarryIn,
CarryOut => CarryOut
);
PROCESS
PROCEDURE CHECK_CarryOut(
next_CarryOut : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (CarryOut /= next_CarryOut) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns CarryOut="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CarryOut);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_CarryOut);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Done(
next_Done : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (Done /= next_Done) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns Done="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Done);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Done);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Output(
next_Output : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (Output /= next_Output) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns Output="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Output);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Output);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 50ns
WAIT FOR 50 ns;
CHECK_CarryOut('0', 50);
CHECK_Done('0', 50);
CHECK_Output('0', 50);
-- -------------------------------------
-- ------------- Current Time: 100ns
WAIT FOR 50 ns;
Reset <= '0';
-- -------------------------------------
-- ------------- Current Time: 200ns
WAIT FOR 100 ns;
Start <= '1';
-- -------------------------------------
-- ------------- Current Time: 250ns
WAIT FOR 50 ns;
CHECK_Done('1', 250);
-- -------------------------------------
-- ------------- Current Time: 300ns
WAIT FOR 50 ns;
Start <= '0';
-- -------------------------------------
-- ------------- Current Time: 400ns
WAIT FOR 100 ns;
CarryIn <= '1';
-- -------------------------------------
-- ------------- Current Time: 500ns
WAIT FOR 100 ns;
Start <= '0';
inA <= "01";
-- -------------------------------------
-- ------------- Current Time: 600ns
WAIT FOR 100 ns;
Start <= '1';
inB <= "00";
-- -------------------------------------
-- ------------- Current Time: 650ns
WAIT FOR 50 ns;
CHECK_CarryOut('1', 650);
-- -------------------------------------
-- ------------- Current Time: 700ns
WAIT FOR 50 ns;
Start <= '0';
-- -------------------------------------
-- ------------- Current Time: 800ns
WAIT FOR 100 ns;
inB <= "01";
-- -------------------------------------
-- ------------- Current Time: 900ns
WAIT FOR 100 ns;
Start <= '1';
-- -------------------------------------
-- ------------- Current Time: 950ns
WAIT FOR 50 ns;
CHECK_Output('1', 950);
WAIT FOR 50 ns;
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
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