library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Hand_Shake is    Port ( Req : in  STD_LOGIC;           Send_Ack : out  STD_LOGIC;           En : out  STD_LOGIC;           Start : out  STD_LOGIC;			  Reset : in STD_LOGIC;           Rec_Ack : in  STD_LOGIC);end Hand_Shake;architecture Structural of Hand_Shake issignal C2Output : STD_LOGIC;signal C1Output : STD_LOGIC;signal Not_C2Output : STD_LOGIC;signal Not_Rec_Ack : STD_LOGIC;COMPONENT C_MULLER_GATE	Port ( C_Input : in  STD_LOGIC_VECTOR (1 downto 0);          Reset : in  STD_LOGIC;          Output : out  STD_LOGIC);End Component;COMPONENT Inverter	PORT ( Input : in STD_LOGIC;			 Output : out STD_LOGIC);End Component;beginC_1: C_MULLER_GATE	PORT MAP (C_Input(1) => Req,				 C_Input(0) => Not_C2Output,				 Reset => Reset,				 Output => C1Output);				 C_2: C_MULLER_GATE	PORT MAP (C_Input(1) => C1Output,				 C_Input(0) => Not_Rec_Ack,				 Reset => Reset,				 Output => C2Output);Inverter_1: Inverter	PORT MAP (Input => C2Output,				 Output => Not_C2Output);				 Inverter_2: Inverter	PORT MAP (Input => Rec_Ack,				 Output => Not_Rec_Ack);En <= C1Output;Start <= C2Output;Send_Ack <= C1Output;end;