------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    23:03:02 05/18/2006 -- Design Name: -- Module Name:    EnableAndStart - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity EnableAndStart is    Port ( InputA : in  STD_LOGIC_VECTOR (1 downto 0);           InputB : in  STD_LOGIC_VECTOR (1 downto 0);           Out_put : out  STD_LOGIC;           Carry_Out : out  STD_LOGIC;           Enable : in  STD_LOGIC;           St : in  STD_LOGIC;           Reset : in  STD_LOGIC;           Done : out  STD_LOGIC			  --RegisterO : out  STD_LOGIC_VECTOR (1 downto 0)
			  );end EnableAndStart;architecture Behavioral of EnableAndStart isCOMPONENT Adder_Register    Port ( Input : in  STD_LOGIC_VECTOR (1 downto 0);           Output : out  STD_LOGIC_VECTOR (1 downto 0);			  Reset : in STD_LOGIC;           Enable : in  STD_LOGIC);End Component;COMPONENT Full_Adder    Port ( inA : in STD_LOGIC_VECTOR (1 downto 0);           inB : in STD_LOGIC_VECTOR (1 downto 0);           Start : in  STD_LOGIC;           Done : out  STD_LOGIC;			  Reset : in STD_LOGIC;           Output : out STD_LOGIC;			  CarryIn : in STD_LOGIC;			  CarryOut : out STD_LOGIC);End Component;signal RegOut : STD_LOGIC_VECTOR (1 downto 0);beginAdder: Full_Adder	PORT MAP (inA(0) => RegOut(0),				 inA(1) => '0',				 inB(0) => RegOut(1),				 inB(1) => '0',				 Start => St,				 Done => Done,				 Reset => Reset,				 Output => Out_put,				 CarryIn => '0',				 CarryOut => Carry_Out);				 R_1: Adder_Register	PORT MAP (Input(1) => InputB(0),				 Input(0) => InputA(0),				 Reset => Reset,				 Output => RegOut,				 Enable => Enable);--RegisterO <= RegOut;end Behavioral;