?? c_element.vhd
字號:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:58 05/17/2006
-- Design Name:
-- Module Name: C_Element - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity C_Element is
end C_Element;
architecture Behavioral of C_Element is
begin
end Behavioral;
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