/* sysLib.c - ARM Integrator system-dependent routines *//* Copyright 1999-2001 ARM Limited *//* Copyright 1999-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01q,28may02,m_h  windML not UGL01p,31oct01,rec  use generic driver for amba timer01o,09oct01,m_h  configure keyboard if windML is configured01n,09oct01,jpd  correct sysPhysMemDesc entres for 946es.01m,03oct01,jpd  tidied slightly01l,28sep01,pr   added support for ARM946E.01k,12sep01,m_h  WindML support01j,27aug01,jb   Adding USB support01i,21feb01,h_k  added support for ARM966ES and ARM966ES_T.01h,01dec00,rec  fix typo in INCLUDE_FEI82557END01g,20nov00,jpd  added support for Intel Ethernet driver.01f,14jun00,pr   fixed Flash enable/disable with recent versions of FPGA.01e,18feb00,jpd  minor tidying. Added Core Module Header sysPhysMemDesc entry.01d,07feb00,jpd  added support for ARM720T, ARM920T.01c,13jan00,pr	 added support for ARM740T.01b,07dec99,pr	 added support for PCI.01a,15nov99,ajb  copied from pid7t version 01o.*//*DESCRIPTIONThis library provides board-specific routines for the ARM IntegratorDevelopment Board BSP.It #includes the following chip drivers:    nullVme.c -         dummy VMEbus routines    ambaTimer.c -       AMBA timer driver    ambaIntrCtl.c -     AMBA interrupt controller driver    primeCellSio.c -	PrimeCell UART driver    pciIomapLib.c -	PCI I/O mapping supportif INCLUDE_FLASH is defined, it #includes:    flashMem.c -        Flash memory driver    nvRamToFlash.c -    driver to use some Flash like NVRAMelse it #includes:    nullNvRam.c -	dummy NVRAM routinesIt #includes the following BSP files:    sysSerial.c -	serial device initialisation routines    sysEnd.c -		END network driver support routines.    pciIomapShow.c -	PCI Show routinesINCLUDE FILES: sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h	       pciIomapLib.hSEE ALSO:.pG "Configuration".I "ARM Architecture Reference Manual,".I "ARM 7TDMI Data Sheet,".I "ARM 720T Data Sheet,".I "ARM 740T Data Sheet,".I "ARM 920T Technical Reference Manual",.I "ARM 940T Technical Reference Manual",.I "ARM 946E-S Technical Reference Manual",.I "ARM 966E-S Technical Reference Manual",.I "ARM Reference Peripherals Specification,".I "ARM Integrator/AP User Guide",.I "ARM Integrator/CM7TDMI User Guide",.I "ARM Integrator/CM720T User Guide",.I "ARM Integrator/CM740T User Guide",.I "ARM Integrator/CM920T User Guide",.I "ARM Integrator/CM940T User Guide",.I "ARM Integrator/CM946E User Guide",.I "ARM Integrator/CM9x6ES Datasheet".*//* includes */#include "vxWorks.h"#include "config.h"#include "sysLib.h"#include "string.h"#include "intLib.h"#include "taskLib.h"#include "vxLib.h"#include "muxLib.h"#include "cacheLib.h"#if defined(CPU_720T)  || defined(CPU_720T_T) || \    defined(CPU_740T)  || defined(CPU_740T_T) || \    defined(CPU_920T)  || defined(CPU_920T_T) || \    defined(CPU_940T)  || defined(CPU_940T_T) || \    defined(CPU_946ES) || defined(CPU_946ES_T)#include "arch/arm/mmuArmLib.h"#include "private/vmLibP.h"#include "dllLib.h"#include "pciIomapLib.h"#endif /* defined(720T/740T/920T/940T/946ES) */#ifdef INCLUDE_WINDML#define INCLUDE_AMBAKEYBOARD#define INCLUDE_AMBAMOUSE#endif/* imports */IMPORT char end [];			    /* end of system, created by ld */IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */#if !defined(INCLUDE_MMU) && \    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))#define INCLUDE_MMU#endif#if defined(INCLUDE_CACHE_SUPPORT)#if defined(CPU_7TDMI) || defined(CPU_7TDMI_T) || \    defined(CPU_966ES) || defined(CPU_966ES_T)       FUNCPTR sysCacheLibInit = NULL;#endif /* defined(CPU_7TDMI/7TDMI_T) */#if	defined(CPU_940T) || defined(CPU_940T_T)UINT32 * sysCacheUncachedAdrs = (UINT32 *)SYS_CACHE_UNCACHED_ADRS;#endif /* defined(CPU_940T/940T_T) */#endif /* defined(INCLUDE_CACHE_SUPPORT) *//* globals */#if defined(INCLUDE_MMU)#if defined(CPU_720T)  || defined(CPU_720T_T) || \    defined(CPU_740T)  || defined(CPU_740T_T) || \    defined(CPU_920T)  || defined(CPU_920T_T) || \    defined(CPU_940T)  || defined(CPU_940T_T) || \    defined(CPU_946ES) || defined(CPU_946ES_T)#if defined(CPU_720T) || defined(CPU_720T_T) || \    defined(CPU_920T) || defined(CPU_920T_T)/* * The following structure describes the various different parts of the * memory map to be used only during initialisation by * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are * defined. * * Clearly, this structure is only needed if the CPU has an MMU! * * The following are not the smallest areas that could be allocated for a * working system. If the amount of memory used by the page tables is * critical, they could be reduced. */PHYS_MEM_DESC sysPhysMemDesc [] =    {    /* adrs and length parameters must be page-aligned (multiples of 0x1000) */    /* DRAM */    {    (void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */    (void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */    ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE    },    /*     * ROM is normally marked as uncacheable by VxWorks. We leave it like that     * for the time being, even though this has a severe impact on execution     * speed from ROM.     */    {    (void *) ROM_BASE_ADRS,    (void *) ROM_BASE_ADRS,    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,#ifdef INCLUDE_FLASH    /* needs to be writable */    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT#else    VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT#endif    },    /*     * I/O space:     * Do not map in all I/O space, only that which has something there.     * Otherwise we will use all of RAM allocating page tables!     */    {    (void *) INTEGRATOR_HDR_BASE,	/* Core Module Header regs */    (void *) INTEGRATOR_HDR_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) INTEGRATOR_SC_BASE,	/* System controller */    (void *) INTEGRATOR_SC_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) INTEGRATOR_EBI_BASE,	/* EBI controller */    (void *) INTEGRATOR_EBI_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#ifdef INCLUDE_SERIAL    {    (void *) UART_0_BASE_ADR,		/* PrimeCell UART */    (void *) UART_0_BASE_ADR,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) UART_1_BASE_ADR,		/* PrimeCell UART */    (void *) UART_1_BASE_ADR,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#endif /* INCLUDE_SERIAL */#ifdef INCLUDE_AMBAKEYBOARD    {    (void *) KBD_BASE_ADR,		/* PrimeCell Keyboard */    (void *) KBD_BASE_ADR,    ROUND_UP (KBD_REGS_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#endif /* INCLUDE_AMBAKEYBOARD */#ifdef INCLUDE_AMBAMOUSE    {    (void *) MOUSE_BASE_ADR,		/* PrimeCell Mouse */    (void *) MOUSE_BASE_ADR,    ROUND_UP (MOUSE_REGS_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#endif /* INCLUDE_AMBAMOUSE */    {    (void *) IC_BASE,		/* Interrupt controller */    (void *) IC_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) AMBA_TIMER_BASE,	/* Counter/Timer */    (void *) AMBA_TIMER_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) LED_BASE,		/* LEDs */    (void *) LED_BASE,    PAGE_SIZE,    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#ifdef INCLUDE_PCI    {    (void *) CPU_PCI_IO_ADRS,	/* PCI I/O space */    (void *) CPU_PCI_IO_ADRS,    ROUND_UP (CPU_PCI_IO_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) CPU_PCI_CNFG_ADRS,	/* PCI Configuration space */    (void *) CPU_PCI_CNFG_ADRS,    ROUND_UP (CPU_PCI_CNFG_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT    },    {    (void *) CPU_PCI_MEM_ADRS,	/* PCI Mem space */    (void *) CPU_PCI_MEM_ADRS,    ROUND_UP (CPU_PCI_MEM_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) V3_BASE,		/* V360EPC register */    (void *) V3_BASE,    ROUND_UP (V3_REGS_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT    },#endif /* INCLUDE_PCI */    {    (void *) INTEGRATOR_MBRD_SSRAM_BASE,    (void *) INTEGRATOR_MBRD_SSRAM_BASE,    ROUND_UP (INTEGRATOR_MBRD_SSRAM_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT    },    /*     * The following entry is for the "real" address of the Core Module     * SDRAM (as opposed to the alias in low memory). The size of the area     * mapped here is for the amount that has been "occluded" by the Core     * Module SSRAM from zero upwards.     */    {    (void *) INTEGRATOR_HDR0_SDRAM_BASE,    (void *) INTEGRATOR_HDR0_SDRAM_BASE,    ROUND_UP (INTEGRATOR_HDR_SSRAM_SIZE, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT    }    };#endif /* defined(CPU_720T/720T_T/920T/920T_T) */#if defined(CPU_740T)  || defined(CPU_740T_T) || \    defined(CPU_940T)  || defined(CPU_940T_T) || \    defined(CPU_946ES) || defined(CPU_946ES_T)/* * The following structure describes the various different regions of the * memory map to be used only during initialisation by * vmMpuGlobalMapInit() when INCLUDE_MMU_MPU is defined. * * On the MPUs, the virtual and physical addresses must be * the same.  In addition, the regions must have an alignment equal to * their size, with a minimum size of 4K.  This restriction is very * important in understanding the region definitions.  Regions cannot be * arbitrarily moved or their size changed without considering * alignment.  There is no page-table RAM overhead to mapping in large * areas of the memory map, but we can only define 8 memory regions in * total. Regions cannot be marked as read-only in VxWorks. * * Here, we (arbitrarily) choose to leave as many regions in the MPU * unused as possible, so that they are available for later use (e.g. to * mark areas of RAM as non-cacheable).  This means that large areas are * mapped in as valid where no memory or I/O devices are actually * present.  If this is not desired, larger numbers of smaller regions * could be defined which more closely match what is actually present in * the memory map (paying close attention to the alignment requirements * mentioned above).  Spurious accesses outside those defined regions * would then cause access violation exceptions when the MPU is switched * on. * * Note that potentially important areas of memory space are currently * unmapped.  Core module alias areas, and the EBI space * (Boot ROM and SSRAM) are not defined, and will therefore cause * access violations. */PHYS_MEM_DESC sysPhysMemDesc [] =    {    /*     * Map the peripheral register area as writable but not cached or     * buffered.     */    {    (void *) INTEGRATOR_PERIPHERAL_BASE,	/* virtual address */    (void *) INTEGRATOR_PERIPHERAL_BASE,	/* physical address */    /* Region must have alignment equal to size, minimum of PAGE_SIZE */    ROUND_UP(INTEGRATOR_PERIPHERAL_SIZE, PAGE_SIZE),	/* length */    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    /*     * Main RAM region from 0 to max(SSRAM,SDRAM), marked cacheable and     * bufferable.     */    {    (void *) 0,	/* virtual address */    (void *) 0,	/* physical address */    /* Region must have alignment equal to size, minimum of PAGE_SIZE */    ROUND_UP ((LOCAL_MEM_SIZE + LOCAL_MEM_LOCAL_ADRS), PAGE_SIZE), /* length */    /* initial state: */    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE    },#if (LOCAL_MEM_LOCAL_ADRS != 0)    /* If (e.g. on 946ES) we have image starting above where the     * tightly-coupled memory is, then put another entry (higher priority than     * the one before), which marks the area taken up by the tightly-coupled     * memory as non-cacheable.     */    /* on-header SSRAM, or tightly-coupled memory */    {    (void *) 0,			/* virtual address */    (void *) 0,			/* physical address */    ROUND_UP (LOCAL_MEM_LOCAL_ADRS, PAGE_SIZE), /* length, then initial state */    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },#endif /* (LOCAL_MEM_LOCAL_ADRS != 0) */    /*     * Flash memory: marked valid and writeable but not cached -     * we need to be able to poll words in the Flash when updating     * contents.     */    {    (void *) ROM_BASE_ADRS,	/* virtual address */