(void *) ROM_BASE_ADRS,	/* physical address */    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),	/* length */    /* initial state: */    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT    },    /* I/O space: */#ifdef INCLUDE_PCI    {    (void *) INTEGRATOR_PCI_BASE,    (void *) INTEGRATOR_PCI_BASE,    ROUND_UP (0x20000000, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    },    {    (void *) CPU_PCI_IO_ADRS,    (void *) CPU_PCI_IO_ADRS,    ROUND_UP (0x4000000, PAGE_SIZE),    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT    }#endif    };#endif /* defined(740T/940T/946ES) */int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);#endif /* defined(CPU_720T/740T/920T/940T/946ES) */#endif /* defined(INCLUDE_MMU) */int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */int	sysProcNum;			/* processor number of this CPU */int	sysFlags;			/* boot flags */char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted *//* locals */#ifdef AMBA_INT_PRIORITY_MAP/* * List of interrupts to be serviced in order of decreasing priority. * Interrupts not in this list will be serviced least-significant bit * first at a lower priority than those in the list. * * To use lowest-bit = highest-priority, reverse the sense of the * condition below so that ambaIntLvlPriMap is a zero pointer. */#if TRUELOCAL int ambaIntLvlPriMap[] =    {    INT_LVL_UART_0,		/* console port */    SYS_TIMER_INT_LVL,		/* sysClk */    INT_LVL_UART_1,		/* second serial port */    AUX_TIMER_INT_LVL,		/* auxClk */#ifdef INCLUDE_AMBAKEYBOARD    INT_LVL_KEYBOARD,           /* keyboard */#endif /* INCLUDE_AMBAKEYBOARD */#ifdef INCLUDE_AMBAMOUSE    INT_LVL_MOUSE,              /* mouse */#endif /* INCLUDE_AMBAMOUSE */#ifdef INCLUDE_PCI    INT_LVL_PCI_0,		/* PCI device 0: */    INT_LVL_PCI_1,		/* PCI device 1: */    INT_LVL_PCI_2,		/* PCI device 2: */    INT_LVL_PCI_3,		/* PCI device 3: */#endif /* INCLUDE_PCI */    -1				/* list terminator */    };#elseLOCAL int *ambaIntLvlPriMap = 0;#endif#else/* * This array maps interrupt levels to mask patterns.  The interrupt level * is the index, the data is the mask value.  A mask bit enables one * level.  The mask value is 'and'd with the ambaIntLvlEnabled value * before writing to the chip. */LOCAL UINT32 ambaIntLvlMask[AMBA_INT_NUM_LEVELS + 1] = /* int level mask */	{	0x00000000,     /* level 0, all disabled */	0x00000001, 0x00000003, 0x00000007, 0x0000000f,	0x0000001f, 0x0000003f, 0x0000007f, 0x000000ff,	0x000001ff, 0x000003ff, 0x000007ff, 0x00000fff,	0x00001fff, 0x00003fff, 0x00007fff, 0x0000ffff,	0x0001ffff, 0x0003ffff, 0x0007ffff, 0x000fffff,	0x001fffff, 0x003fffff  /* level 22, all enabled */	};#if AMBA_INT_NUM_LEVELS != 22#   error ambaIntLvlMask is wrong size for number of levels#endif#endif	/* ifdef AMBA_INT_PRIORITY_MAP *//* defines *//* externals */IMPORT int  ambaIntDevInit (void);IMPORT void sysIntStackSplit (char *, long);/* globals *//* forward LOCAL functions declarations *//* forward declarations */char *	sysPhysMemTop (void);#if defined (INCLUDE_USB)void sysUsbPciInit(void);#endif/* included source files */#ifdef INCLUDE_FLASH#include "mem/nvRamToFlash.c"#include "flashMem.c"#else#include "mem/nullNvRam.c"#endif#include "vme/nullVme.c"#include "sysSerial.c"#include "timer/ambaTimer.c"#include "primeCellSio.c"#include "intrCtl/ambaIntrCtl.c"#include "pciIomapLib.c"#include "pciIomapShow.c"#include "sysEnd.c"#ifdef INCLUDE_WINDML#include "ambaKbd.c"#include "ambaMse.c"#include "sysWindML.c"#endif /* INCLUDE_WINDML *//********************************************************************************* sysModel - return the model name of the CPU board** This routine returns the model name of the CPU board.** NOTE* This routine does not include all of the possible variants, and the* inclusion of a variant in here does not mean that it is supported.** RETURNS: A pointer to a string identifying the board and CPU.*/char *sysModel (void)    {#if	defined(CPU_7TDMI)    return	"ARM Integrator - ARM7TDMI (ARM)";#elif	defined(CPU_7TDMI_T)    return	"ARM Integrator - ARM7TDMI (Thumb)";#elif	defined(CPU_720T)    return	"ARM Integrator - ARM720T (ARM)";#elif	defined(CPU_720T_T)    return	"ARM Integrator - ARM720T (Thumb)";#elif	defined(CPU_740T)    return	"ARM Integrator - ARM740T (ARM)";#elif	defined(CPU_740T_T)    return	"ARM Integrator - ARM740T (Thumb)";#elif	defined(CPU_920T)    return	"ARM Integrator - ARM920T (ARM)";#elif	defined(CPU_920T_T)    return	"ARM Integrator - ARM920T (Thumb)";#elif	defined(CPU_940T)    return	"ARM Integrator - ARM940T (ARM)";#elif	defined(CPU_940T_T)    return	"ARM Integrator - ARM940T (Thumb)";#elif   defined(CPU_946ES)    return      "ARM Integrator - ARM946ES (ARM)";#elif   defined(CPU_946ES_T)    return      "ARM Integrator - ARM946ES (Thumb)";#elif   defined(CPU_966ES)    return      "ARM Integrator - ARM966ES (ARM)";#elif   defined(CPU_966ES_T)    return      "ARM Integrator - ARM966ES (Thumb)";#else#error CPU not supported#endif	/* defined(CPU_7TDMI) */    }/********************************************************************************* sysBspRev - return the BSP version with the revision eg 1.2/<x>** This function returns a pointer to a BSP version with the revision.* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the* BSP identification string.** RETURNS: A pointer to the BSP version/revision string.*/char * sysBspRev (void)    {    return (BSP_VERSION BSP_REV);    }#if defined(CPU_720T)  || defined(CPU_720T_T) || \    defined(CPU_740T)  || defined(CPU_740T_T) || \    defined(CPU_920T)  || defined(CPU_920T_T) || \    defined(CPU_940T)  || defined(CPU_940T_T) || \    defined(CPU_946ES) || defined(CPU_946ES_T)/********************************************************************************* sysHwInit0 - perform early BSP-specific initialisation** This routine performs such BSP-specific initialisation as is necessary before* the architecture-independent cacheLibInit can be called. It is called* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS* has been cleared.** RETURNS: N/A*/void sysHwInit0 (void)    {#ifdef INCLUDE_CACHE_SUPPORT    /*     * Install the appropriate cache library, no address translation     * routines are required for this BSP, as the default memory map has     * virtual and physical addresses the same.     */#if	defined(CPU_720T) || defined(CPU_720T_T)    cacheArm720tLibInstall (NULL, NULL);#elif   defined(CPU_740T) || defined(CPU_740T_T)    cacheArm740tLibInstall (NULL, NULL);#elif   defined(CPU_920T) || defined(CPU_920T_T)    cacheArm920tLibInstall (NULL, NULL);#elif   defined(CPU_940T) || defined(CPU_940T_T)    cacheArm940tLibInstall (NULL, NULL);#elif   defined(CPU_946ES) || defined(CPU_946ES_T)    cacheArm946eLibInstall (NULL, NULL);#endif#endif /* INCLUDE_CACHE_SUPPORT */#if defined(INCLUDE_MMU)    /* Install the appropriate MMU library and translation routines */#if	defined(CPU_720T) || defined(CPU_720T_T)    mmuArm720tLibInstall (NULL, NULL);#elif   defined(CPU_740T) || defined(CPU_740T_T)    mmuArm740tLibInstall (NULL, NULL);#elif   defined(CPU_920T) || defined(CPU_920T_T)    mmuArm920tLibInstall (NULL, NULL);#elif   defined(CPU_940T) || defined(CPU_940T_T)    mmuArm940tLibInstall (NULL, NULL);#elif   defined(CPU_946ES) || defined(CPU_946ES_T)    mmuArm946eLibInstall (NULL, NULL);#endif#endif /* defined(INCLUDE_MMU) */    return;    }#endif /* defined(720T/740T/920T/940T/946ES) */#if defined(INCLUDE_PCI)/********************************************************************************* sysV3Init - initialise the V3 PCI bridge controller** This function initialises the V3 chip which controls the PCI bridge.** RETURNS: N/A*/void sysV3Init (void)    {    volatile int i, j;    /* setting this register will take the V3 out of reset */    *(UINT32 *)(INTEGRATOR_SC_PCIENABLE) = 1;    /* wait a few usecs to settle the device and the PCI bus (no timers yet) */    for (i = 0; i < 100 ; i++)	   j = i + 1;    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */    *(UINT16 *)(V3_BASE + V3_LB_IO_BASE) = (UINT16)(V3_BASE >> 16);    do	{        *(UINT8 *)(V3_BASE + V3_MAIL_DATA) = 0xAA;	*(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;	}    while (*(UINT8 *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||	    *(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);    /* Make sure that V3 register access is not locked, if it is, unlock it */    if ((*(UINT16 *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK) ==							    V3_SYSTEM_M_LOCK)	*(UINT16 *)(V3_BASE + V3_SYSTEM) = 0xA05F;    /*     * Ensure that the slave accesses from PCI are disabled while we     * setup windows     */    *(UINT16 *)(V3_BASE + V3_PCI_CMD) &=    				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */    *(UINT16 *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;    /* Make all accesses from PCI space retry until we're ready for them */    *(UINT16 *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;    /*     * Set up any V3 PCI Configuration Registers that we absolutely have to     * LB_CFG controls Local Bus protocol.     * Enable LocalBus byte strobes for READ accesses too.     * set bit 7 BE_IMODE and bit 6 BE_OMODE     */    *(UINT16 *)(V3_BASE + V3_LB_CFG) |= 0x0C0;    /*     * PCI_CMD controls overall PCI operation.     * Enable PCI bus master.     */    *(UINT16 *)(V3_BASE + V3_PCI_CMD) |= 0x04;    /*     * PCI_MAP0 controls where the PCI to CPU memory window is on the Local Bus     */    *(UINT32 *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |					(V3_PCI_MAP_M_ADR_SIZE_512M |					V3_PCI_MAP_M_REG_EN |					V3_PCI_MAP_M_ENABLE);    /* PCI_BASE0 is the PCI address of the start of the window */    *(UINT32 *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;    /* PCI_MAP1 is LOCAL address of the start of the window */    *(UINT32 *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |			 V3_PCI_MAP_M_ENABLE);    /* PCI_BASE1 is the PCI address of the start of the window */    *(UINT32 *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;    /*     * Set up the windows from local bus memory into PCI configuration,     * I/O and Memory.     * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.     */    *(UINT16 *)(V3_BASE +V3_LB_BASE2) =    			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;    *(UINT16 *)(V3_BASE + V3_LB_MAP2) = 0;    /*     * PCI Configuration, use LB_BASE1/LB_MAP1.     *     * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1     * Map first 256Mbytes as non-prefetchable via BASE0/MAP0     * (INTEGRATOR_PCI_BASE == PCI_MEM_BASE)     */    *(UINT32 *)(V3_BASE + V3_LB_BASE0) =    			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);    *(UINT16 *)(V3_BASE + V3_LB_MAP0) =    				((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */    *(UINT32 *)(V3_BASE + V3_LB_BASE1) =    			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);