/* sysEnd.c - System Enhanced network interface support library *//* Copyright 1997-2002 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01k,16jul02,m_h  dc driver load string changes (78869)01j,25apr02,to   fix PCI to CPU offset address01i,03dec01,rec  fix compiler warnings01h,09jul01,jpd  fixed compilation warning.01g,09apr01,rec  fix 559 initialization problem01f,22jan01,jmb  add support for Intel InBusiness 10/100 PCI Network Adapter01e,20nov00,jpd  added Intel Ethernet driver (FEI) support; added use of		 DEC_USR_SF to do 100 Mbits/s; modified DEC driver support.01d,17feb00,jpd  minor comments corrections.01c,07feb00,jpd  tidied.01b,07dec99,pr   support for PCI/DEC21x4x01a,10nov99,ajb  created based on version 01a from pid7t.*//*DESCRIPTIONThis file contains the board-specific routines for Ethernet adapterinitialisation of Intel (formerly DEC) 21040, 21140 and 21143-basedadapters and Intel Pro 100+ based adapters.NOTEAt the time of writing, this module has only been tested with the followingEthernet cards:    21040 controller: Digital DE435.    21140 controller: D-Link DFE-500TX                      Kingston KNE-100TX    21143 controller: Intel (formerly DEC) EB143 evaluation card.                      Kingston KNE-100TX                      Longshine 8038 TXD    82559 controller: Intel PRO/100+ Management Adapter                      Intel InBusiness 10/100 PCI Network AdapterRefer to the BSP reference entry for any eventual limitations orproblems related to the BSP.SEE ALSO: ifLib,.I "Digital Semiconductor 21143 PCI/CardBus Fast Ethernet LAN Controller,".I "Digital Semiconductor 21143 10/100Base-TX Evaluation Board User's Guide,".I "Intel 10/100 MBit Ethernet Family Software technical Reference Manual."*/#include "vxWorks.h"#include "config.h"#include "cacheLib.h"#include "stdio.h"#ifdef INCLUDE_END#include "drv/end/dec21x40End.h"#include "drv/end/fei82557End.h"/* defines */#undef  SYS_FEI_DEBUG#define CSR_BASE_MSK	0x7f		/* Mask Base Address Register */#define	END_LD_STR_SIZE	80/* PCI memory base address register configuration mode */#define FORCE		0x00	/* overwrite membase address register */#define AUTO		0x01	/* read membase address register *//* * Need to use automatic configuration mode using the resource assigning in * pciAssignResources(). */#define PCI_REG_MOD	AUTO	/* define the register configuration mode */#define TYPE_ALLOC	1000/* * DEC cards in range 1 -> 1000 */#define DEC_START	1/* DEC 21X4X 10/100Base-TX Board type */#define	EB143		DEC_START + 1	/* DEC 21143 10/100Base-TX */#define	DC140		DEC_START + 2	/* DEC 21140 10/100Base-TX */#define	DC040		DEC_START + 3	/* DEC 21040 10/100Base-TX *//* Untested types are > 100 */#define LC82C168	DEC_START + 104	/* Lite-On PNIC */#define MX98713		DEC_START + 105	/* Macronix 98713 PMAC */#define MX98715		DEC_START + 106	/* Macronix 98715 PMAC */#define AX88140		DEC_START + 107	/* ASIX AX88140 */#define PNIC2		DEC_START + 108	/* Lite-On PNIC-II */#define COMET		DEC_START + 109	/* Comet family */#define COMPEX9881	DEC_START + 110	/* Compex 9881 */#define I21145		DEC_START + 111	/* Intel 21145 *//* * FEI cards in range 1001 -> 2000 */#define FEI_START	TYPE_ALLOC + 1#define PRO100B		FEI_START	/* Intel EtherExpress PRO-100B PCI */#define INBUSINESS	FEI_START + 1	/* Intel InBusiness 10/100 PCI */#define XX82559ER 	FEI_START + 100	/* Arbitrary card with 82559ER *//* * DEC driver user flags * * Use of the SF (Store and Forward) bit is necessary at the time of * writing on current boards to support 100 Mbits/s operation, though * it is not necessary for 10 Mbits/s. */#define DEC_USR_FLAGS_143 	(DEC_USR_21143 | DEC_USR_SF)#define DEC_USR_FLAGS_140 	(DEC_USR_BAR_RX	| \                                 DEC_USR_RML	| \                                 DEC_USR_CAL_08 | \				 DEC_USR_PBL_04 | \				 DEC_USR_21140	| \				 DEC_USR_SF)#define DEC_USR_FLAGS_040 	(DEC_USR_BAR_RX | \                                 DEC_USR_CAL_08 | \				 DEC_USR_PBL_04)/* These are untested */#define PNIC_USR_FLAGS	  	(DEC_USR_21143)#define PNIC2_USR_FLAGS	  	(DEC_USR_PNIC2)#define MX98713_USR_FLAGS	(0)#define MX98715_USR_FLAGS	(0)#define AX88140_USR_FLAGS	(0)#define COMET_USR_FLAGS		(0)#define COMET_USR_FLAGS		(0)#define COMET_USR_FLAGS		(0)#define COMPEX9881_USR_FLAGS	(0)#define I21145_USR_FLAGS	(0)/* END table information */#define DEC_BUFF_LOAN   1                       /* enable buffer loaning *//* DEC 21X4X PCI/CardBus specific definitions */#define DEC21X4X_PCI_VENDOR_ID		0x1011	/* PCI vendor ID */#define DEC21143_PCI_DEVICE_ID		0x0019	/* PCI device ID */#define DEC21140_PCI_DEVICE_ID		0x0009	/* PCI device ID */#define DEC21040_PCI_DEVICE_ID		0x0002	/* PCI device ID */#define PNIC_PCI_VENDOR_ID		0x11AD	/* PCI vendor ID */#define PNIC_PCI_DEVICE_ID		0x0002#define PNIC2_PCI_DEVICE_ID		0xc115#define MACRONIX_PCI_VENDOR_ID		0x10d9	/* PCI vendor ID */#define MX98713_PCI_DEVICE_ID		0x0512#define MX98715_PCI_DEVICE_ID		0x0531#define ASIX_PCI_VENDOR_ID		0x125B	/* PCI vendor ID */#define AX88140_PCI_DEVICE_ID		0x1400#define COMET_PCI_VENDOR_ID			0x1317	/* PCI vendor ID */#define COMET1_PCI_DEVICE_ID		0x0981#define COMET2_PCI_DEVICE_ID		0x0985#define COMET3_PCI_DEVICE_ID		0x1985#define COMPEX_PCI_VENDOR_ID		0x11F6	/* PCI vendor ID */#define COMPEX9881_PCI_DEVICE_ID	0x9881#define INTEL_PCI_VENDOR_ID		0x8086	/* PCI vendor ID */#define I21145_PCI_DEVICE_ID		0x0039#define DAVICOM_PCI_VENDOR_ID		0x1282	/* PCI vendor ID */#define DAVICOM9100_PCI_DEVICE_ID	0x9100#define DAVICOM9102_PCI_DEVICE_ID	0x9102#define ACCTON_PCI_VENDOR_ID		0x1113	/* PCI vendor ID */#define EN1217_PCI_DEVICE_ID		0x1217#define	BOARD_TYPE_NB			(NELEMENTS(boardResources))#ifdef INCLUDE_FEI82557END/* EEPROM control bits */#define EE_SK           0x01            /* shift clock */#define EE_CS           0x02            /* chip select */#define EE_DI           0x04            /* chip data in */#define EE_DO           0x08            /* chip data out *//* EEPROM opcode */#define EE_CMD_WRITE    0x05            /* WRITE opcode, 101 */#define EE_CMD_READ     0x06            /* READ  opcode, 110 */#define EE_CMD_ERASE    0x07            /* ERASE opcode, 111 *//* EEPROM misc. defines */#define EE_CMD_BITS     3               /* number of opcode bits */#define EE_ADDR_BITS    6               /* number of address bits */#define EE_DATA_BITS    16              /* number of data bits */#define EE_SIZE         0x40            /* 0x40 words */#define EE_CHECKSUM     0xbaba          /* checksum *//* PC compatibility macros */#define sysOutWord(addr,data)   (*((UINT16 *) (addr)) = ((UINT16) (data)))#define sysInWord(addr)         (*((UINT16 *) (addr)))#define sysOutLong(addr,data)   (*((UINT32 *) (addr)) = ((UINT32) (data)))#define sysInLong(addr)         (*((UINT32 *) (addr)))#define FEI_MEMSIZE0            0x00001000#define FEI_INIT_STATE_MASK     (-1)    /* unused */#define FEI_INIT_STATE          (-1)    /* unused */#define UNKNOWN                 (-1)/* 82557/9 PCI specific definitions *//* Intel PRO-100B PCI specific definitions */#ifndef PRO100B_PCI_VENDOR_ID#define PRO100B_PCI_VENDOR_ID   0x8086  /* PCI vendor ID */#define PRO100B_PCI_DEVICE_ID   0x1229  /* PCI device ID */#endif    /* PRO100B_PCI_VENDOR_ID *//* Intel InBusiness 10/100 PCI specific definitions */#ifndef INBUSINESS_PCI_VENDOR_ID#define INBUSINESS_PCI_VENDOR_ID   PRO100B_PCI_VENDOR_ID  /* PCI vendor ID */#define INBUSINESS_PCI_DEVICE_ID   0x1030                 /* PCI device ID */#endif    /* INBUSINESS_PCI_VENDOR_ID */#endif /* INCLUDE_FEI82557END *//* typedefs */typedef struct pciResource              /* PCI_RESOURCES */    {    UINT32      iobaseCsr;              /* Base Address Register 0 */    UINT32      membaseCsr;             /* Base Address Register 1 */    char        irq;                    /* Interrupt Request Level */    UINT32	irqvec;			/* Interrupt Request vector */    UINT32      configType;             /* type of configuration */    void *	buf;			/* any allocated buffer space */    UINT32	cpuToPciOffset;		/* Any offset from CPU to PCI address */    } PCI_RESOURCES;typedef struct boardResource		/* BOARD_RESOURCES */    {    UINT32	type;			/* type of the board */    UINT32	vendorId;		/* Vendor ID */    UINT32	deviceId;		/* Device ID */    UINT32	decUsrFlags;		/* DEC driver user flags */    } BOARD_RESOURCES;#ifdef INCLUDE_FEI82557ENDtypedef struct feiResource              /* FEI_RESOURCE */    {    UINT32      membaseCsr;             /* Base Address Register 0 */    UINT32      iobaseCsr;              /* Base Address Register 1 */    UINT32      membaseFlash;           /* Base Address Register 2 */    char        irq;                    /* Interrupt Request Level */    UINT32      configType;             /* type of configuration - unused */    UINT32      boardType;              /* type of LAN board this unit is */    UINT16      eeprom[0x40];           /* Ethernet Address of this unit */    INT32       timeout;                /* timeout for the self-test */    INT32	str[2];			/* storage for the self-test result */    volatile INT32 * pResults;		/* pointer to the self-test result */    UINT        memLength;              /* required memory size */    UINT        initialStateMask;       /* mask parameter to vmStateSet */    UINT        initialState;           /* state parameter to vmStateSet */    } FEI_RESOURCE;#endif/* locals *//* * This array defines the board-specific PCI resources, the base address * register configuration mode and the Ethernet adapter type. It's indexed * using the device number returned from pciFindDevice(). * * The mode is set as AUTO so this will be erased by the configuration read * from the card that is effectively set by pciAssignResources(). See * sysLanPciInit() for this. */LOCAL PCI_RESOURCES pciResources [INTEGRATOR_MAX_END_DEVS] =    {    {PCI_IO_ADR0, PCI_MEM_ADR0, PCI_INT_LVL0, PCI_INT_VEC0, PCI_REG_MOD, 0, 0},    {PCI_IO_ADR1, PCI_MEM_ADR1, PCI_INT_LVL1, PCI_INT_VEC1, PCI_REG_MOD, 0, 0},    {PCI_IO_ADR2, PCI_MEM_ADR2, PCI_INT_LVL2, PCI_INT_VEC2, PCI_REG_MOD, 0, 0}    };/* * This array defines board-specific vendor and device ids, flags to pass to * the drive load routine and the function used to select the media. */LOCAL BOARD_RESOURCES boardResources [] =    {#ifdef INCLUDE_DEC21X40END    {EB143, DEC21X4X_PCI_VENDOR_ID, DEC21143_PCI_DEVICE_ID, DEC_USR_FLAGS_143},    {DC140, DEC21X4X_PCI_VENDOR_ID, DEC21140_PCI_DEVICE_ID, DEC_USR_FLAGS_140},    {DC040, DEC21X4X_PCI_VENDOR_ID, DEC21040_PCI_DEVICE_ID, DEC_USR_FLAGS_040},#ifdef INCLUDE_DEC_UNTESTED    /* Untested cards */    {LC82C168, PNIC_PCI_VENDOR_ID, PNIC_PCI_DEVICE_ID, PNIC_USR_FLAGS},    {PNIC2, PNIC_PCI_VENDOR_ID, PNIC2_PCI_DEVICE_ID, PNIC2_USR_FLAGS},    {MX98713, MACRONIX_PCI_VENDOR_ID, MX98713_PCI_DEVICE_ID, MX98713_USR_FLAGS},    {MX98715, MACRONIX_PCI_VENDOR_ID, MX98715_PCI_DEVICE_ID, MX98715_USR_FLAGS},    {AX88140, ASIX_PCI_VENDOR_ID, AX88140_PCI_DEVICE_ID, AX88140_USR_FLAGS},    {COMET, COMET_PCI_VENDOR_ID, COMET1_PCI_DEVICE_ID, COMET_USR_FLAGS},    {COMET, COMET_PCI_VENDOR_ID, COMET2_PCI_DEVICE_ID, COMET_USR_FLAGS},    {COMET, COMET_PCI_VENDOR_ID, COMET3_PCI_DEVICE_ID, COMET_USR_FLAGS},    {COMPEX9881, COMPEX_PCI_VENDOR_ID, COMPEX9881_PCI_DEVICE_ID,\     COMPEX9881_USR_FLAGS},    {I21145, INTEL_PCI_VENDOR_ID, I21145_PCI_DEVICE_ID, I21145_USR_FLAGS},    {DC140, DAVICOM_PCI_VENDOR_ID, DAVICOM9100_PCI_DEVICE_ID,\     DEC_USR_FLAGS_140},    {DC140, DAVICOM_PCI_VENDOR_ID, DAVICOM9102_PCI_DEVICE_ID,\     DEC_USR_FLAGS_140},    {MX98715, ACCTON_PCI_VENDOR_ID, EN1217_PCI_DEVICE_ID, MX98715_USR_FLAGS},#endif /* INCLUDE_DEC_UNTESTED */#endif /* INCLUDE_DEC21X40END */#ifdef INCLUDE_FEI82557END    {PRO100B, PRO100B_PCI_VENDOR_ID, PRO100B_PCI_DEVICE_ID, 0},    {INBUSINESS, INBUSINESS_PCI_VENDOR_ID, INBUSINESS_PCI_DEVICE_ID, 0},#ifdef INCLUDE_FEI_UNTESTED    {XX82559ER, PRO100B_PCI_VENDOR_ID, I82559ER_PCI_DEVICE_ID, 0},#endif#endif /* INCLUDE_FEI82557END */    };/* END load strings */LOCAL char	endLoadStr[INTEGRATOR_MAX_END_DEVS][END_LD_STR_SIZE];/* Index of devices */LOCAL int       currentEndDevice        = 0;#ifdef INTEGRATOR_ENET_FIXED_BUF_ADRSLOCAL UINT32 sysEnetBufAdrs[] =    {    INTEGRATOR_ENET_PRIMARY_BUF_ADRS,    INTEGRATOR_ENET_SECONDARY_BUF_ADRS,    INTEGRATOR_ENET_TERTIARY_BUF_ADRS    };#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */#ifdef INCLUDE_FEI82557ENDLOCAL FEI_RESOURCE feiResources [INTEGRATOR_MAX_END_DEVS] =    {    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,     UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,     UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,     UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE}    };LOCAL const char * phys[] =    {    "None", "i82553-A/B", "i82553-C", "i82503",    "DP83840", "80c240", "80c24", "i82555",    "unknown-8", "unknown-9", "DP83840A", "unknown-11",    "unknown-12", "unknown-13", "unknown-14", "unknown-15"    };enum phy_chips    {    NonSuchPhy=0, I82553AB, I82553C, I82503,    DP83840, S80C240, S80C24, I82555, DP83840A=10, UndefinedPhy    };LOCAL const char *connectors[] = {" RJ45", " BNC", " AUI", " MII"};#endif /* INCLUDE_FEI82557END *//* imports *//* End device table - should be INTEGRATOR_MAX_END_DEVS+1 entries */IMPORT END_TBL_ENTRY	endDevTbl[];#ifdef INCLUDE_DEC21X40END/* DEC specific imports */IMPORT END_OBJ * 	dec21x40EndLoad (char *, void *);IMPORT int		dec21x40Loops;#endif#ifdef INCLUDE_FEI82557END/* FEI specific imports */IMPORT FUNCPTR  feiEndIntConnect;IMPORT FUNCPTR  feiEndIntDisconnect;IMPORT END_OBJ* fei82557EndLoad (char *, void *);IMPORT void	sysFlashBoardDelay (void);/* forward declarations */LOCAL UINT16    sys557eepromRead (int unit, int location);LOCAL UINT32    sys557mdioRead   (int unit, int phyId, int location);LOCAL UINT32    sys557mdioWrite  (int unit, int phyId, int location, int value);LOCAL int       sys557IntEnable  (int unit);LOCAL int       sys557IntDisable (int unit);LOCAL int       sys557IntAck     (int unit);#endif /* INCLUDE_FEI82557END *//********************************************************************************* sysLanPciInit - prepare LAN adapter for initialization** This routine find out the PCI device, and map its memory and I/O address.* It will understand both DEC21x4x and FEI type cards.** RETURNS: N/A*/STATUS sysLanPciInit (void)    {    PCI_RESOURCES *	pRsrc;		/* dec resource */    UINT32		pciBus;		/* PCI Bus number */    UINT32		pciDevice;	/* PCI Device number */    UINT32		pciFunc;	/* PCI Function number */    unsigned int	ix;		/* counter */    int			iy;		/* counter */    int			unit = 0;	/* unit numbers */    UINT32		boardType = NONE; /* board type detected */#ifdef INCLUDE_FEI82557END    FEI_RESOURCE *      pFeiRes;        /* FEI specific info */#endif#ifdef INCLUDE_DEC21X40END    /*     * Set the loops to be less per nano-second since this board is slower,     * than say, EBSA-285.     */    dec21x40Loops = 1;#endif