---實(shí)驗(yàn)十二 序列檢測器
--DETECT.VHD
--用于檢測序列"1110010"

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DETECT is
  port (
     InputS,CLK: in    std_logic; 
     GOT_N: out    std_logic
  ); 
end DETECT;

architecture a of DETECT is
TYPE state_TYPE IS(S0,S1,S2,S3,S4,S5,S6,S7); --八個(gè)狀態(tài)類型
SIGNAL present_state,next_state:state_TYPE;  --每個(gè)狀態(tài)又有當(dāng)前和下一個(gè)信號之分
SIGNAL OutputS: std_logic;
BEGIN
state_comb:PROCESS(present_state,InputS)
BEGIN
   CASE present_state IS
      WHEN S0=>  OutputS<='0';
         IF InputS='1' THEN       -- Detect first bit 1
             next_state<=S1;      --detected
         ELSE
             next_state<=S0;
         END IF;


      WHEN S1=>  OutputS<='0';
         IF InputS='1' THEN       -- Detect 2nd bit 1
             next_state<=S2;
         ELSE
             next_state<=S0;
         END IF;

      WHEN S2=>  OutputS<='0'; -- Detect 3rd bit 1
         IF InputS= '1' THEN
             next_state<=S3;
         ELSE
             next_state<=S0;
         END IF;

      WHEN S3=>  OutputS<='0';-- Detect 4th bit 0
         IF InputS= '1' THEN   
                             
             next_state<=S3;
         -- not detected,backto s3,since we have got 1111,
         --maybe next bit is 0,so we get 1110 from the 2nd bit
         ELSE
             next_state<=S4;
         END IF;

      WHEN S4=>  OutputS<='0';  -- Detect 5th bit 0
         IF InputS= '1' THEN
             next_state<=S1;
         ELSE
             next_state<=S5;
         END IF;

      WHEN S5=>  OutputS<='0';  -- Detect 6th bit 1
         IF InputS= '1' THEN
             next_state<=S6;
         ELSE
             next_state<=S0; 
        -- if not ,back to s0,since none will be fit other than the s0
         END IF;

     WHEN S6=>  OutputS<='0';  -- Detect 7th bit 0
         IF InputS= '1' THEN
             next_state<=S2;
         ELSE
             next_state<=S7;
         END IF;

     WHEN S7=>  OutputS<='1';   --we have got the code
         IF InputS= '1' THEN    -- if 1,maybe the next cycle, to s1
             next_state<=S1;     
         ELSE
             next_state<=S0; -- if 0,maybe the next cycle, to s0
         END IF;
   END CASE;

END PROCESS state_comb;

GOT_N<=NOT OutputS;---FOR EASY TO SHOW ON THE LOW_LEVEL SENSITIVE LED


PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
    present_state<=next_state;
END IF;
END PROCESS;
end a;