LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY singt IS
	PORT
	(
		CLK			:	IN 	STD_LOGIC;	--//信號源時鐘
		DOUT		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)	--//8位波形數據輸出
	);
END;

ARCHITECTURE DACC OF singt IS
	COMPONENT data_rom	--//調用波形數據存儲器LPM_ROM文件：data_rom.vhd
		PORT
		(
			address		:	IN	STD_LOGIC_VECTOR(5 DOWNTO 0);	--//6位地址信號
			inclock		:	IN	STD_LOGIC;						--//地址鎖存時鐘
			q			:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
	END COMPONENT;

		SIGNAL Q1 : STD_LOGIC_VECTOR(5 DOWNTO 0);	--//內部節點作為地址計數器
		
	BEGIN
			
		---------------------------
		PROCESS (CLK)
		BEGIN
			IF CLK'EVENT AND CLK= '1' THEN
				Q1<=Q1+1;
			END IF;
		END PROCESS;

	u1:data_rom PORT MAP(address=>Q1,q=>DOUT,inclock=>CLK);--//例化
END DACC;


             next_state<=S4;
         END IF;

      WHEN S4=>  OutputS<='0';  -- Detect 5th bit 0
         IF InputS= '1' THEN
             next_state<=S1;
         ELSE
             next_state<=S5;
         END IF;

      WHEN S5=>  OutputS<='0';  -- Detect 6th bit 1
         IF InputS= '1' THEN
             next_state<=S6;
         ELSE
             next_state<=S0; 
        -- if not ,back to s0,since none will be fit other than the s0
         END IF;

     WHEN S6=>  OutputS<='0';  -- Detect 7th bit 0
         IF InputS= '1' THEN
             next_state<=S2;
         ELSE
             next_state<=S7;
         END IF;

     WHEN S7=>  OutputS<='1';   --we have got the code
         IF InputS= '1' THEN    -- if 1,maybe the next cycle, to s1
             next_state<=S1;     
         ELSE
             next_state<=S0; -- if 0,maybe the next cycle, to s0
         END IF;
   END CASE;

END PROCESS state_comb;

GOT_N<=NOT OutputS;---FOR EASY TO SHOW ON THE LOW_LEVEL SENSITIVE LED


PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
    present_state<=next_state;
END IF;
END PROCESS;
end a;