?? cstartup_ads.s
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;***********************************************************
;The company of TONGSHI, Xi'an
;File Name： DVB_T.s
;Description：
;Author： Weixichao
;Date： 2006.4.1
;***********************************************************
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
IRQ_STACK_SIZE EQU 36
FIQ_STACK_SIZE EQU 24
ABT_STACK_SIZE EQU 4
UND_STACK_SIZE EQU 4
SVC_STACK_SIZE EQU 4
USER_STACK_SIZE EQU 400
;------------------------------------------------------------------------------
;- Stack Area Definition
;------------------------------------------------------------------------------
AREA |C$$stack|, DATA
;- IRQ stack definition
AT91_IRQ_Stack_End DCD 0x55AA55AA
SPACE (IRQ_STACK_SIZE - 4)
AT91_IRQ_Stack_Begin EQU (AT91_IRQ_Stack_End + (IRQ_STACK_SIZE - 4))
;- FIQ stack definition
AT91_FIQ_Stack_End DCD 0x55AA55AA
SPACE (FIQ_STACK_SIZE - 4)
AT91_FIQ_Stack_Begin EQU (AT91_FIQ_Stack_End + (FIQ_STACK_SIZE - 4))
;- ABORT stack definition
AT91_ABT_Stack_End DCD 0x55AA55AA
SPACE (ABT_STACK_SIZE - 4)
AT91_ABT_Stack_Begin EQU (AT91_ABT_Stack_End + (ABT_STACK_SIZE - 4))
;- UNDEF stack definition
AT91_UND_Stack_End DCD 0x55AA55AA
SPACE (UND_STACK_SIZE - 4)
AT91_UND_Stack_Begin EQU (AT91_UND_Stack_End + (UND_STACK_SIZE - 4))
;- SVC stack definition
AT91_SVC_Stack_End DCD 0x55AA55AA
SPACE (SVC_STACK_SIZE-4)
AT91_SVC_Stack_Begin EQU (AT91_SVC_Stack_End + (SVC_STACK_SIZE-4))
;- USER and SYSTEM stack definition
AT91_USER_Stack_End DCD 0x55AA55AA
SPACE (USER_STACK_SIZE-4)
AT91_USER_Stack_Begin EQU (AT91_USER_Stack_End + (USER_STACK_SIZE-4))
;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
;------------------------------------------------------------------------------
AREA dvb_t, CODE, READONLY
EXPORT __ENTRY
__ENTRY
;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors are read at address 0.
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;------------------------------------------------------------------------------
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
fiqvec
B fiqvec ; FIQ,read the AIC
;-------------------
;- The initreset handler
;-------------------
InitReset
ldr r1, = AT91_SVC_Stack_Begin
bic r1, r1, #3 ; Insure word alignement
mov sp, r1 ; Init stack SYS
;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------
;- The processor will remain in the last initialized mode.
;------------------------------------------------------------------------------
;- Load the stack base addresses
add r0, pc,#-(8+.-StackData) ; @ where to read values (relative)
ldmia r0, {r1-r6}
;- Set up Supervisor Mode and set SVC Mode Stack
msr cpsr_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
bic r1, r1, #3 ; Insure word alignement
mov sp, r1 ; Init stack SYS
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
bic r2, r2, #3 ; Insure word alignement
mov sp, r2 ; Init stack IRQ
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
bic r3, r3, #3 ; Insure word alignement
mov sp, r3 ; Init stack FIQ
;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
bic r4, r4, #3 ; Insure word alignement
mov sp, r4 ; Init stack Abort
;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
bic r5, r5, #3 ; Insure word alignement
mov sp, r5 ; Init stack Undef
;- Set up user Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_SYS:OR:I_BIT:OR:F_BIT
bic r6, r6, #3 ; Insure word alignement
mov sp, r6 ; Init stack Undef
b EndInitStack
StackData
DCD AT91_SVC_Stack_Begin
DCD AT91_IRQ_Stack_Begin
DCD AT91_FIQ_Stack_Begin
DCD AT91_ABT_Stack_Begin
DCD AT91_UND_Stack_Begin
DCD AT91_USER_Stack_Begin
EndInitStack
add r2, pc,#-(8+.-CInitData) ; @ where to read values (relative)
ldmia r2, {r0, r1, r3, r4}
cmp r0, r1 ; Check that they are different
beq EndRW
LoopRW
cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRW
EndRW
mov r2, #0
LoopZI
cmp r3, r4 ; Zero init
strcc r2, [r3], #4
bcc LoopZI
b EndInitC
CInitData
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; Top of zero init segment
DCD |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
DCD |Image$$RW$$Base| ; Base of RAM to initialise
DCD |Image$$ZI$$Base| ; Base and limit of area
DCD |Image$$ZI$$Limit| ; Top of zero init segment
EndInitC
;********************
mov r0,#0x0004a000
add r0,r0,#0x30000004
mov r1,#0xff000000
add r1,r1,#0x00ff0000
add r1,r1,#0x0000fd00
str r0,[r1,#0x44]
mov r0,#0x00000001
str r0,[r1,#0x200] ;WTD close and remap
mov r0,#0x00000081
add r0,r0,#0x00000100
sub r1,r1,#0x100
str r0,[r1]
mov r0,#0x00000600
str r0,[r1,#0x4]
mov r0,#0x00007000
add r0,r0,#0x00000014
str r0,[r1,#0x10] ;使能TC.ADC.PIO時(shí)鐘
mov r0,#0x00000100
add r0,r0,#0x00000001
str r0,[r1,#0x20]
mov r0,#0x007d0000 ;*******************
add r0,r0,#0x10000000
add r0,r0,#0x00000017
str r0,[r1,#0x2c] ;晶振用18.432MHz
mov r0,#0x00000007
str r0,[r1,#0x30]
str r0,[r1,#0x40] ;pck0****************
mov r0,#0x00000700
add r0,r0,#0x0000000d
str r0,[r1,#0x64] ;配置時(shí)鐘和PMC
sub r1,r1,#0x800 ;r1=0xfffff400
mov r0,#0x00000053
add r0,r0,#0x00118000
add r0,r0,#0x3c000000
str r0,[r1,#0x4]
str r0,[r1,#0x14]
str r0,[r1,#0x24]
str r0,[r1,#0x74]
str r0,[r1,#0x64] ;將PIO口配置成TC0.TC1.TC2.pck0=mck.IRQ0,PA0.1.4.6.15.16.20.26.27.28.29
mov r0,#0xffffffbf
str r0,[r1,#0x34]
mov r1,#0xff000000
add r1,r1,#0x00ff0000
add r1,r1,#0x0000f000
mov r0,#0x00000027
str r0,[r1,#0x10]
str r0,[r1,#120] ;中斷模式
adrl r0,spihandler0
str r0,[r1,#0x90]
adrl r0,spihandler1
str r0,[r1,#0xf8] ;此處填入中斷處理函數(shù)入口地址
add r1,r1,#0x00000100
mov r0,#0x40000010
str r0,[r1,#0x20]
mvn r0,r0
str r0,[r1,#0x24] ;中斷使能與禁止
mov r0,#0x00000000
str r0,[r1,#0x38] ;調(diào)試時(shí)對(duì)AIC配置
mov r1,#0xff000000
add r1,r1,#0x00fd0000
add r1,r1,#0x00008000
mov r0,#0x00000001
str r0,[r1]
mov r0,#0x00000021
add r0,r0,#0x02000000
add r0,r0,#0x00040000
add r0,r0,#0x00000800
str r0,[r1,#0x4] ;adc mode
mov r0,#0x00000030
str r0,[r1,#0x10]
mov r0,#0x00040000
str r0,[r1,#0x24] ;interrupt condition endrx
mov r0,#0x00200000
add r0,r0,#0x2000
str r0,[r1,#0x100]
mov r0,#0x00000500
str r0,[r1,#0x104]
mov r0,#0x00000001
str r0,[r1,#0x120] ;use the PDC
mov r1,#0xff000000
add r1,r1,#0x00fa0000
mov r0,#0x00000039
str r0,[r1,#0xc4]
mov r0,#0x00000001
str r0,[r1]
mov r0,#0x00000002
add r0,r0,#0x0000c100
add r0,r0,#0x00890000
add r0,r0,#0x89000000
str r0,[r1,#0x4]
mov r0,#0x00000064
add r0,r0,#0x00001b00
str r0,[r1,#0x1c]
mov r0,r0,lsr#0x1
str r0,[r1,#0x14]
str r0,[r1,#0x18]
mov r0,#00000002
str r0,[r1,#0x24] ;tc0
mov r0,#0x00000004
str r0,[r1] ;tc0 triger
mrs r8,cpsr
and r8,r8,#0xffffff3f ;設(shè)置CPSR中斷位I=0,F=0
msr cpsr_cxsf,r8
End
mov r4,#0xa5000000
add r4,r4,#0x00000001
mov r5,#0xff000000
add r5,r5,#0x00ff0000
add r5,r5,#0x0000fd00
str r4,[r5,#0x40] ;重新啟動(dòng)看門狗
b End
spihandler0
stmfd sp!, {r0-r4,r8-r9,lr}
mov r1,#0xff000000
add r1,r1,#0x00fd0000
add r1,r1,#0x00008000
mov r0,#0x00200000
add r0,r0,#0x2000
str r0,[r1,#0x100]
mov r0,#0x00000500
str r0,[r1,#0x104]
mov r0,#0xff000000
add r0,r0,#0x00ff0000
add r0,r0,#0x0000f400
mov r1,#0x00000008
str r1,[r0]
str r1,[r0,#0x10]
mov r4,#2
aa0
mov r1,#0x00000008
str r1,[r0,#0x34]
mov r2,#0xff
mov r3,#0xff000
aa1
sub r2,r2,#0x1
add r2,r2,#0x1
subs r3,r3,#0x1
bne aa1
mov r1,#0x00000008
str r1,[r0,#0x30]
mov r2,#0xff
mov r3,#0xff000
aa2
sub r2,r2,#0x1
add r2,r2,#0x1
subs r3,r3,#0x1
bne aa2
subs r4,r4,#0x1
bne aa0 ;the led shining two times
mrs r8,spsr
and r8,r8,#0xffffff3f ;設(shè)置CPSR中斷位I=0,F=0
msr spsr_cxsf,r8
mov r9,#0xff000000
add r9,r9,#0x00ff0000
add r9,r9,#0x0000f000
str r9,[r9,#0x130] ;結(jié)束前對(duì)AIC_EOICR130寫值
ldmfd sp!, {r0-r4,r8-r9,lr}
subs pc,lr,#4 ;SPI中斷返回
spihandler1
stmfd sp!, {r0-r4,r8-r9,lr}
mov r0,#0xff000000
add r0,r0,#0x00ff0000
add r0,r0,#0x0000f400
mov r1,#0x00000004
str r1,[r0]
str r1,[r0,#0x10]
mov r4,#2
aa00
mov r1,#0x00000004
str r1,[r0,#0x34]
mov r2,#0xff
mov r3,#0xff000
aa11
sub r2,r2,#0x1
add r2,r2,#0x1
subs r3,r3,#0x1
bne aa11
mov r1,#0x00000004
str r1,[r0,#0x30]
mov r2,#0xff
mov r3,#0xff000
aa22
sub r2,r2,#0x1
add r2,r2,#0x1
subs r3,r3,#0x1
bne aa22
subs r4,r4,#0x1
bne aa00 ;the led shining two times
mrs r8,spsr
and r8,r8,#0xffffff3f ;設(shè)置CPSR中斷位I=0,F=0
msr spsr_cxsf,r8
mov r9,#0xff000000
add r9,r9,#0x00ff0000
add r9,r9,#0x0000f000
str r9,[r9,#0x130] ;結(jié)束前對(duì)AIC_EOICR130寫值
ldmfd sp!, {r0-r4,r8-r9,lr}
subs pc,lr,#4 ;SPI中斷返回
END
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