else if( node->v.p[0]->nodetype == en_labcon)
                {
                ap1 = xalloc(sizeof(AMODE));
                ap1->mode = am_direct;
                ap1->offset = makenode(node->v.p[0]->nodetype,(char *)node->v.p[0]->v.i,0);
                do_extend(ap1,ssize,size,flags);
                make_legal(ap1,flags,psize);
                return ap1;
                }
				else if (node->v.p[0]->nodetype == en_absacon) {
								ap1 = xalloc(sizeof(AMODE));
								ap1->mode = am_direct;
								ap1->offset = makenode(en_absacon,(char *)((SYM *)node->v.p[0]->v.p[0])->value.i,0);
                do_extend(ap1,ssize,size,flags);
                make_legal(ap1,flags,psize);
                return ap1;

				}
				else if (node->v.p[0]->nodetype == en_regref) {
        	ap1 = gen_expr(node->v.p[0],F_ALL,4);
          do_extend(ap1,ssize,size,flags);
          make_legal(ap1,flags,psize);
					return ap1;
				}
        ap1 = gen_expr(node->v.p[0],F_DREG | F_IMMED,4); /* generate address */
        if( ap1->mode == am_dreg )
                {
                ap1->mode = am_indisp;
								ap1->offset = makenode(en_icon,0,0);
          			do_extend(ap1,ssize,size,flags);
        				make_legal(ap1,flags,psize);
                return ap1;
                }
        ap1->mode = am_direct;
        do_extend(ap1,ssize,size,flags);
        make_legal(ap1,flags,psize);
        return ap1;
}

AMODE    *gen_unary(ENODE *node,int flags,int size,int op, int fop)
/*
 *      generate code to evaluate a unary minus or complement.
 */
{       AMODE    *ap;
        ap = gen_expr(node->v.p[0],F_FREG | F_DREG | F_VOL,size);
				if (ap->mode == am_freg) {
					gen_code(fop,0,0,0);
					ap = fstack();
				}
				else {
        	gen_code(op,size,ap,0);
				}
        make_legal(ap,flags,size);
        return ap;
}

AMODE    *gen_binary(ENODE *node,int flags,int size,int op, int fop)
/*
 *      generate code to evaluate a binary node and return 
 *      the addressing mode of the result.
 */
{       AMODE    *ap1, *ap2;
				if (size > 4) {
        	ap1 = gen_expr(node->v.p[0],F_VOL | F_FREG,size);
					mark();
        	ap2 = gen_expr(node->v.p[1],F_MEM | F_FREG,size);
					if (ap2->mode == am_freg)
						gen_code(fop,0,0,0);
					else {
						int t;
						t = natural_size(node->v.p[1]);
						if (t== 0) t = size;
						if (t <=4)
							if (fop == op_fadd)
								fop = op_fiadd;
							else
								fop = op_fisub;
						gen_f10code(fop,t,ap2,0);
					}
					ap1 = fstack();
				}
				else {
        	ap1 = gen_expr(node->v.p[0],F_VOL | F_DREG,size);
					mark();
        	ap2 = gen_expr(node->v.p[1],F_ALL,size);
        	gen_code(op,size,ap1,ap2);
				}
        freeop(ap2);
				release();
        make_legal(ap1,flags,size);
        return ap1;
}

AMODE    *gen_xbin(ENODE *node,int flags,int size,int op, int fop)
/*
 *      generate code to evaluate a restricted binary node and return 
 *      the addressing mode of the result.
 */
{       AMODE    *ap1, *ap2;
				if (size > 4) {
        	ap1 = gen_expr(node->v.p[0],F_VOL | F_FREG,size);
					mark();
        	ap2 = gen_expr(node->v.p[1],F_MEM | F_FREG,size);
					if (ap2->mode == am_freg)
						gen_code(fop,0,0,0);
					else
						gen_code(fop,size,ap2,0);
					ap1 = fstack();
				}
				else {
        	ap1 = gen_expr(node->v.p[0],F_VOL | F_DREG,size);
					mark();
        	ap2 = gen_expr(node->v.p[1],F_ALL,size);
        	gen_code(op,size,ap2,ap1);
				}
				release();
        freeop(ap2);
        make_legal(ap1,flags,size);
        return ap1;
}
void doshift(AMODE *ap1, AMODE *ap2, int size, int op)
{       AMODE   *ecx = makedreg(ECX), *eax = makedreg(EAX);
				if (ap2->mode == am_immed) {
					gen_code2(op,size,1,ap1,ap2);
				}
				else
					if (ap1->mode == am_dreg && ap1->preg == ECX) {
							if (ap2->mode == am_dreg) {
								gen_code(op_xchg,4,ap2,ap1);
								gen_code2(op,size,1,ap2,ecx);
								gen_code(op_xchg,4,ap2,ap1);
							}
							else {
								if (regs[0])
									gen_push(EAX,am_dreg,0);
								gen_code(op_xchg,4,eax,ecx);
								gen_code(op_mov,1,ap2,ecx);
								gen_code2(op,size,1,eax,ecx);
								gen_code(op_xchg,4,eax,ecx);
								if (regs[0])
									gen_pop(EAX,am_dreg,0);
							}
					}
					else
						if (ap2->mode == am_dreg) {
							if (ap2->preg != ECX)
								gen_code(op_xchg,4,ap2,ecx);
							gen_code2(op,size,1,ap1,ecx);
							if (ap2->preg != ECX)
								gen_code(op_xchg,4,ap2,ecx);
						}
						else {
							if (regs[1])
								gen_push(ECX,am_dreg,0);
							gen_code(op_mov,4,ap2,ecx);
							gen_code2(op,size,1,ap1,ecx);
							if (regs[1])
								gen_pop(ECX,am_dreg,0);
						}
}
AMODE    *gen_shift(ENODE *node, int flags, int size, int op)
/*
 *      generate code to evaluate a shift node and return the
 *      address mode of the result.
 */
{       AMODE    *ap1, *ap2;
        ap1 = gen_expr(node->v.p[0],F_DREG | F_VOL,size);
				mark();
        ap2 = gen_expr(node->v.p[1],F_DREG | F_IMMED,natural_size(node->v.p[1]));
				doshift(ap1,ap2,size,op);
        freeop(ap2);
				release();
        make_legal(ap1,flags,size);
        return ap1;
}
void dodiv(AMODE *ap1, AMODE *ap2, int size, int op,int modflag)
{
	AMODE *eax = makedreg(EAX), *edx = makedreg(EDX), *ecx = makedreg(ECX);
	if (ap2->mode == am_immed) {
		ap2 = make_muldivval(ap2);
	}
	if (ap1->preg != EAX) {
		int temp;
		gen_code(op_xchg,4,eax,ap1);
		if (ap1->mode == am_dreg && ap2->mode == am_dreg && ap1->preg == ap2->preg) {
			gen_code(op,4,eax,0);
			gen_code(op_xchg,4,eax,ap1);
			return;
		}
		temp = regs[0];
		regs[0] = regs[ap1->preg];
		regs[ap1->preg] = temp;
	}
	if (ap2->preg == EDX) {
		if (regs[1])
			gen_push(ECX,am_dreg,0);
		if (regs[2])
			gen_push(EDX,am_dreg,0);
		gen_code(op_mov,4,ecx,edx);
		gen_code(op_sub,4,edx,edx);
		gen_code(op,4,ecx,0);
		if (modflag)
			gen_code(op_xchg,4,eax,edx);
		if (regs[2])
			gen_pop(EDX,am_dreg,0);
		if (regs[1])
			gen_pop(ECX,am_dreg,0);
	}
	else {
		if (regs[2])
			gen_push(EDX,am_dreg,0);
		gen_code(op_sub,4,edx,edx);
		gen_code(op,4,ap2,0);
		if (modflag)
			gen_code(op_xchg,4,eax,edx);
		if (regs[2])
			gen_pop(EDX,am_dreg,0);
	}
	if (ap1->preg != EAX) {
		int temp;
		gen_code(op_xchg,4,eax,ap1);
		temp = regs[0];
		regs[0] = regs[ap1->preg];
		regs[ap1->preg] = temp;
	}
}
void domul(AMODE *ap1, AMODE *ap2, int size, int op)
{
	AMODE *eax = makedreg(EAX), *edx = makedreg(EDX), *ecx = makedreg(ECX);
	if (ap2->mode == am_immed) {
		ap2 = make_muldivval(ap2);
	}
	if (ap1->preg != EAX) {
		int temp;
		gen_code(op_xchg,4,eax,ap1);
		if (ap1->mode == am_dreg && ap2->mode == am_dreg && ap1->preg == ap2->preg && ap1->preg != EDX) {
			gen_code(op,4,eax,0);
			gen_code(op_xchg,4,eax,ap1);
			return;
		}
		temp = regs[0];
		regs[0] = regs[ap1->preg];
		regs[ap1->preg] = temp;
	}
	if (ap2->preg == EDX) {
		if (regs[1])
			gen_push(ECX,am_dreg,0);
		if (regs[2])
			gen_push(EDX,am_dreg,0);
		gen_code(op_mov,4,ecx,edx);
		gen_code(op_sub,4,edx,edx);
		gen_code(op,4,ecx,0);
		if (regs[2])
			gen_pop(EDX,am_dreg,0);
		if (regs[1])
			gen_pop(ECX,am_dreg,0);
	}
	else {
		if (regs[2])
			gen_push(EDX,am_dreg,0);
		gen_code(op,4,ap2,0);
		if (regs[2])
			gen_pop(EDX,am_dreg,0);
	}
	if (ap1->preg != EAX) {
		int temp;
		gen_code(op_xchg,4,eax,ap1);
		temp = regs[0];
		regs[0] = regs[ap1->preg];
		regs[ap1->preg] = temp;
	}
}
AMODE    *gen_modiv(ENODE *node, int flags, int size, int op, int modflag)
/*
 *      generate code to evaluate a mod operator or a divide
 *      operator. these operations are done on only long
 *      divisors and word dividends so that the 68000 div
 *      instruction can be used.
 */
{       AMODE    *ap1, *ap2;
				
				if (size > 4) {
					ap1 = gen_expr(node->v.p[0],F_FREG | F_VOL,size);
					ap2 = gen_expr(node->v.p[1],F_ALL,size);
					op = op_fdiv;
					if (ap2->mode == am_freg)
						gen_code(op,0,0,0);
					else {
						int t;
						t = natural_size(node->v.p[1]);
						if (t== 0) t = size;
						if (t <=4)
							op = op_fidiv;
						gen_f10code(op,t,ap2,0);
					}
					ap1 = fstack();
					do_extend(ap1,10,size,flags);
					make_legal(ap1,flags,size);
					return ap1;
				}
					if (op == op_idiv) {
  	      	ap1 = gen_expr(node->v.p[0],F_DREG | F_VOL,-4);
					}
					else {
        		ap1 = gen_expr(node->v.p[0],F_DREG | F_VOL,4);
					}
					mark();
					if (op == op_idiv) {
    	    	ap2 = gen_expr(node->v.p[1],F_ALL,-4);
					}
					else {
        		ap2 = gen_expr(node->v.p[1],F_ALL,4);
					}
					dodiv(ap1,ap2,size,op,modflag);
					freeop(ap2);
					release();
        	make_legal(ap1,flags,size);
        	return ap1;
					
}


void swap_nodes(ENODE *node)
/*
 *      exchange the two operands in a node.
 */
{       ENODE    *temp;
        temp = node->v.p[0];
        node->v.p[0] = node->v.p[1];
        node->v.p[1] = temp;
}

AMODE * gen_pdiv(ENODE *node, int flags, int size)
{
				return gen_modiv(node,flags,size,op_div,FALSE);
}			
AMODE * gen_pmul(ENODE *node, int flags, int size)
{
				return gen_mul(node,flags,size,op_mul);
}			
AMODE    *gen_mul(ENODE *node, int flags, int size, int op)
/*
 *      generate code to evaluate a multiply node. both operands
 *      are treated as words and the result is long and is always
 *      in a register so that the 68000 mul instruction can be used.
 */
{       AMODE    *ap1, *ap2;

				if (isintconst(node->v.p[0]->nodetype))
					swap_nodes(node);				
				if (size > 4) {
					ap1 = gen_expr(node->v.p[0],F_FREG | F_VOL,size);
					ap2 = gen_expr(node->v.p[1],F_ALL,size);
					op = op_fmul;
					if (ap2->mode == am_freg)
						gen_code(op,0,0,0);
					else {
						int t;
						t = natural_size(node->v.p[1]);
						if (t== 0) t = size;
						if (t <=4)
							op = op_fimul;
						gen_f10code(op,t,ap2,0);
					}
					ap1 = fstack();
					do_extend(ap1,10,size,flags);
					make_legal(ap1,flags,size);
					return ap1;
				}
					if (op == op_imul) {
      	  	ap1 = gen_expr(node->v.p[0],F_DREG | F_VOL,-4);
					}
					else {
	        	ap1 = gen_expr(node->v.p[0],F_DREG | F_VOL,4);
					}
					mark();
					if (op == op_imul) {
    	    	ap2 = gen_expr(node->v.p[1],F_ALL,-4);
					}
					else {
        		ap2 = gen_expr(node->v.p[1],F_ALL,4);
					}
					domul(ap1,ap2,size,op);
					freeop(ap2);
					release();
					do_extend(ap1,4,size,flags);
        	make_legal(ap1,flags,size);
        	return ap1;
}
AMODE    *gen_hook(ENODE *node, int flags, int size)
/*
 *      generate code to evaluate a condition operator node (?:)
 */
{       AMODE    *ap1, *ap2;
        int             false_label, end_label;
        false_label = nextlabel++;
        end_label = nextlabel++;
        flags = (flags & (F_AREG | F_DREG)) | F_VOL;
        falsejp(node->v.p[0],false_label);
        node = node->v.p[1];
        ap1 = gen_expr(node->v.p[0],flags,size);
        freeop(ap1);
        gen_code(op_jmp,0,make_label(end_label),0);
        gen_label(false_label);
        ap2 = gen_expr(node->v.p[1],flags,size);
        if( !equal_address(ap1,ap2) )
                {
                freeop(ap2);
                temp_data();
                gen_code(op_mov,size,ap2,ap1);
                }
        gen_label(end_label);
        return ap1;
}

void floatstore(AMODE *ap, int size, int flags)
{
	if (size <= 4)
						if (flags & F_NOVALUE)
						  gen_codef(op_fistp,size,ap,0);
						else
						  gen_codef(op_fist,size,ap,0);
	else
						if (flags & F_NOVALUE)
						  gen_codef(op_fstp,size,ap,0);
						else
						  gen_codef(op_fst,size,ap,0);
}
AMODE    *gen_asadd(ENODE *node, int flags, int size, int op, int fop)
/*
 *      generate a plus equal or a minus equal node.