/******************************************************************/
/* regs.h	v1.00										    	  */
/* 版權(quán)(c)	2003-   	北京合眾達電子技術(shù)有限責(zé)任公司	    	  */
/* 設(shè)計者:	段立鋒												  */
/******************************************************************/
/******************************************************************/
/* DEFINE ALL PERIPHERAL MEMORY MAPPED REGISTER ADRESSES          */
/******************************************************************/

/******************************************************************/
/* Check to see if mmregs.h has been previously included by       */
/* another header, if so, skip this and go on                     */
/******************************************************************/
#if !defined(__MMREGS)
#include <limits.h>

/******************************************************************/
/* Target specific data and macros                                */
/*                                                                */
/* MASK_TARGET_WORD - bit pattern to mask all bits in a target    */
/*                    word                                        */
/* WORD_SIZE        - size in bits of target word                 */
/* BASE_ADDR        - base address of memory-mapped peripheral    */
/*                    control registers                           */
/******************************************************************/

#define MASK_TARGET_WORD	0xffff
#define TARGET_WRD_SZ	CHAR_BIT	
#define BYTES_PER_WORD  TARGET_WRD_SZ/8
#define WORD_SIZE	(CHAR_BIT * sizeof(unsigned int))


#define TDM_ADDR		TSPC
#define TIMER_ADDR		TCR_ADDR


/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS                                                            */
/*----------------------------------------------------------------------------*/


/******************************************************************/
/* Define data structures for all memory mapped registers         */
/******************************************************************/
/*----------------------------------------------------------------*/
/* Define bit fields for Serial Port Control Registers            */
/*----------------------------------------------------------------*/

#define RSRFULL		13
#define RSRFULL_SZ	 1

#define XSREMPTY	12
#define XSREMPTY_SZ	 1



#define IN1		 9
#define IN1_SZ		 1

#define IN0		 8
#define IN0_SZ		 1


#define TXM		 5
#define TXM_SZ		 1

#define MCM		 4
#define MCM_SZ		 1

#define FSM		 3
#define FSM_SZ		 1

#define FO		 2
#define FO_SZ		 1

#define TDM		 0
#define TDM_SZ		 1

#define CLKDV		 0
#define CLKDV_SZ	 5

#define FSP		 5
#define FSP_SZ		 1

#define CLKP		 6
#define CLKP_SZ		 1

#define FE		 7
#define FE_SZ		 1

#define FIG		 8
#define FIG_SZ		 1

#define PCM		 9
#define PCM_SZ		 1

#define BXE		10
#define BXE_SZ		 1

#define XH		11
#define XH_SZ		 1

#define HALTX		12
#define HALTX_SZ	 1

#define BRE		13
#define BRE_SZ		 1

#define RH		14
#define RH_SZ		 1

#define HALTR		15
#define HALTR_SZ	 1

/******************************************************************/
/* Define Timer Period, and Control Registers with all related    */
/* data structures, macros, and functions                         */
/*----------------------------------------------------------------*/
#define PSC		 6
#define PSC_SZ		 4

#define TRB		 5
#define TRB_SZ		 1

#define TSS		 4
#define TSS_SZ		 1

#define TDDR		 0
#define TDDR_SZ		 4

/*---------------------------------------------------------------*/
/* Data structures, macros for Clock Mode Register               */
/*---------------------------------------------------------------*/

#define PLLMUL		12
#define PLLMUL_SZ	 4

#define PLLDIV		11
#define PLLDIV_SZ	 1

#define PLLCOUNT	 3
#define PLLCOUNT_SZ	 8

#define PLLON_OFF	 2
#define PLLON_OFF_SZ	 1

#define PLLNDIV		 1
#define PLLNDIV_SZ	 1

#define PLLSTATUS	 0
#define PLLSTATUS_SZ	 1


/******************************************************************/
/* Define bit fields for Software Wait State Register             */
/******************************************************************/
#define IO		12
#define IO_SZ		 3

#define DATA_HI		 9
#define DATA_HI_SZ	 3

#define DATA_LO		 6
#define DATA_LO_SZ	 3

#define PROGRAM_HI	 3
#define PROGRAM_HI_SZ	 3

#define PROGRAM_LO	 0
#define PROGRAM_LO_SZ	 3

/*-------------------------------------------------------------------*/
/* Define structure for Bank Switch Control Register                 */
/*-------------------------------------------------------------------*/
#define BNKCMP		12
#define BNKCMP_SZ	 4

#define PSDS		11
#define PSDS_SZ		 1

#define BH		 1
#define BH_SZ		 1

#define EXIO		 0
#define EXIO_SZ		 1

#define INT0		 0
#define INT1		 1
#define INT2		 2
#define TINT		 3

#define RINT0		 4
#define XINT0		 5

#define RINT2		 6
#define XINT2		 7

#define INT3		 8
#define HPINT		 9
#define RINT1		10
#define XINT1		11

#define DMAC0		6
#define DMAC1		7
#define DMAC2		10
#define DMAC3		11
#define DMAC4		12
#define DMAC5		13

/***************************************************************/
/* DEFINE DATA STRUCTURE FOR HOST PORT INTERFACE CONTROL REG   */
/***************************************************************/
#define BOB			 0
#define SMOD		 1
#define DSPINT		 2
#define HINT		 3


#define __MMREGS
#endif