library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
	port(
		 clk: in std_logic;
		 clk1000,clk50: out std_logic
		);
end div;

architecture div_1 of div is
signal y2,y1: std_logic;
  begin
	process(clk)   --1KHz分頻器
	  variable count1: integer range 0 to 499;
	  begin
		if(clk'event and clk='1')then
			if(count1=499)then
				count1:=0;
				y1<=not y1;
			else
				count1:=count1+1;
			end if;
		end if;
		clk1000<=y1;
	end process;
	
	process(y1)    --50Hz分頻器
	  variable count2: integer range 0 to 9;
	  begin
		if(y1'event and y1='1')then
			if(count2=9)then
				count2:=0;
				y2<=not y2;
			else
				count2:=count2+1;
			end if;
		end if;
		clk50<=y2;
	end process;
	end;