library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity modelctrl is
	port(
		 model: in std_logic;
		 stanum: out std_logic_vector(6 downto 0);
		 ctrl: out std_logic_vector(2 downto 0)
		);
end modelctrl;

architecture modelctrl_1 of modelctrl is
signal model1: integer range 0 to 4;
 begin
	process(model,model1)
	  begin
		if(model'event and model='1')then
			if(model1=4)then
				model1<=0;
			else
				model1<=model1+1;
			end if;
		end if;
		if(model1=0)then
			ctrl<="100";
			stanum<="1110111";
		elsif(model1=1)then
			ctrl<="010";
			stanum<="1111100";
		elsif(model1=2)then
			ctrl<="001";
			stanum<="0111001";
		elsif(model1=3)then
			ctrl<="011";
			stanum<="1011110";
		elsif(model1=4)then
			ctrl<="111";
			stanum<="1111001";
		else
			ctrl<="000";
			stanum<="0111111";
		end if;
	end process;
end modelctrl_1;