?? washer_statement.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity washer_statement is
port(
s_and_p,clk50,nextsta_w,power_w: in std_logic;
pause_w: out std_logic;
statectrl: in std_logic_vector(2 downto 0);
count_w: out std_logic_vector(5 downto 0)
);
end washer_statement;
architecture washer_statement_1 of washer_statement is
type state_type is (ready,wash1,wash2,wash3,wash4);
signal present_state,next_state: state_type;
signal s: std_logic;
begin
process(present_state)
begin
case present_state is
when ready => if statectrl(2)='1' then next_state<=wash1;
elsif statectrl(1)='1' then next_state<=wash2;
elsif statectrl(0)='1' then next_state<=wash3;
else next_state<=ready;
end if;
when wash1 => if statectrl(1)='1' then next_state<=wash2;
elsif statectrl(0)='1' then next_state<=wash3;
else next_state<=wash4;
end if;
when wash2 => if statectrl(0)='1' then next_state<=wash3;
else next_state<=wash4;
end if;
when wash3 => next_state<=wash4;
when wash4 => next_state<=ready;
when others => next_state<=ready;
end case;
end process;
process(clk50,nextsta_w)
begin
--if( clk50'event and clk50='1' )then
if (nextsta_w'event and nextsta_w='1') then
present_state<=next_state;
end if;
--end if;
end process;
process(present_state,s_and_p)
begin
case present_state is
when ready => if(power_w='0')then
s<='1';
else
if(s_and_p='1')then
s<='0';
else
s<='1';
end if;
end if;
count_w<="000000";
when wash1 => if (s_and_p'event and s_and_p='1') then
if (s='0') then
s<='1';
else
s<='0';
end if;
end if;
count_w<="010100";
when wash2 => if (s_and_p'event and s_and_p='1') then
if (s='0') then
s<='1';
else
s<='0';
end if;
end if;
count_w<="011110";
when wash3 => if (s_and_p'event and s_and_p='1') then
if (s='0') then
s<='1';
else
s<='0';
end if;
end if;
count_w<="001111";
when wash4 => count_w<="000101";
when others => count_w<="000000";
end case;
pause_w<=s;
end process;
end washer_statement_1;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -